Elliptic Curve Cryptography Processor Research Articles

Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime [Formula: see text] is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye’s double and add (DAA) algorithm based on [Formula: see text]-only common [Formula: see text] (co-[Formula: see text]) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47[Formula: see text]ms at a maximum frequency of 327[Formula: see text]MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and [Formula: see text] metrics.

A High-Performance Elliptic Curve Cryptographic Processor of SM2 over GF(p)

Elliptic curve cryptography (ECC) is widely used in practical applications because ECC has far fewer bits for operands at the same level of security than other public-key cryptosystems such as RSA. The performance of an ECC processor is usually determined by modular multiplication (MM) and point multiplication (PM) operations. For recommended prime field, MM operation can consist of multiplication and fast reduction operations. In this paper, a 256-bit multiplication operation is implemented by a 129-bit (half-word) multiplier using Karatsuba–Ofman multiplication algorithm. The fast reduction is a modulo operation, which gets 512-bit input data from multiplication and outputs a 256-bit result ( 0 ≤ Z < p ) . We propose a two-stage fast reduction algorithm (TSFR) over SCA-256 prime field, which can obtain an intermediate result of 0 ≤ Z < 2 p instead of 0 ≤ Z < 14 p in traditional algorithm, avoiding a lot of repetitive subtraction operations. The PM operation is implemented in width nonadjacent form (NAF) algorithm and its operational schedules are improved to increase the parallelism of multiplication and fast reduction operations. Synthesized with a 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library, the proposed processor costs an area of 280 k gates and PM operation takes 0.057 ms at the frequency of 250 MHz. The design is also implemented on Xilinx Virtex-6 platform, which consumes 27.655 k LUTs and takes 0.37 ms to perform one 256-bit PM operation, attaining six times speed-up over the state-of-the-art. The processor makes a tradeoff between area and performance, thus it is better than other methods.

High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication

In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom–Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 $\mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $\mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works.

FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field

Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level.

Efficient Hardware Implementation of Modular Arithmetic and Group Operation Over Prime Field

The need for secure communication over the network has increased drastically over recent years, and Elliptic Curve Cryptography (ECC) carries out a significant role in moving secured information. In this work, a hardware implementation of modular arithmetic and group operations over the prime field for an Elliptic Curve Cryptography Processor (ECP) for an efficient security system is proposed. The modular addition or subtraction operation takes only one clock cycle and the modular multiplication, which is designed using the interleaved modular multiplication method, requires 257 clock cycles. For elliptic curve group operation separate point doubling (PD) and point addition (PA) architectures are implemented in Jacobean coordinates. These new architectures are simulated in a Xilinx ISE 14.7. After that, the architectures are implemented in Xilinx Virtex-7 field-programmable gate array (FPGA) with the VHDL language. Proposed modular arithmetic and group operations can be utilized to design an Elliptic Curve Point Multiplication (ECPM).

High-performance ECC processor architecture design for IoT security applications

In recent years, the usage of elliptic curve cryptography (ECC) in IoT applications is steadily increasing. The end nodes in IoT applications demand optimized device performance in terms of reduced power consumption and improved computing speed while not compromising on the security of the connected devices. ECC provides better security standards compared with many conventional cryptographic algorithms providing further scope to optimize the performance parameters. This work focuses on improving the key parameters like computing speed, area required for hardware implementation of ECC and demonstrates an efficient way of using the hardware resource sharing and scheduling mechanisms in elliptic curve group operations in affine coordinates which is crucial for implementation of scalar multiplication over prime field $$\mathbb {F}_{p}$$ . With the proposed scalar multiplication hardware architecture, we have achieved a good area-delay product and a significant reduction in cycle count when compared with other reported designs using the same affine coordinates. The proposed architecture has been implemented with 256 bits in both Xilinx Kintex-7 and Virtex-7 FPGA devices. The FPGA synthesis results show that a throughput of 68.52 kbps at a clock frequency of 124.2 MHz is achieved for $$\mathbb {F}_{256}$$ and the computation time is reduced around 1 ms without using any DSP slices.

Low-Complexity Elliptic Curve Cryptography Processor Based on Configurable Partial Modular Reduction Over NIST Prime Fields

We proposed a high-performance elliptic curve cryptography (ECC) processor over NIST prime fields. Instead of applying a full modular reduction to a $2{k}$ -bit product, the proposed partial modular reduction method iteratively performs reductions on partial products whose bit length is slightly greater than ${k}$ , where ${k}$ is the bit length of field elements. As a result, the computational complexity of modular multiplication (MM) was significantly reduced. Moreover, the amount of computation is configurable by parameterizing the size of the partial products. This is a very desirable characteristic of the proposed ECC processor, because the hardware complexity and processing time of the entire ECC processor can be adjusted according to the requirements of various Internet of Things environments. Including the proposed MM module, finite field operation modules are integrated into a single module to further reduce the required resources. The proposed ECC processor synthesized using 180-nm CMOS process technology can perform a 256-bit elliptic curve point multiplication in 0.20–0.74 ms with 144.8k–65.4k gate counts. These results and the experimental results in various FPGA devices show that the proposed ECC processor has significantly better throughput per area than the previously reported ones.

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.

A Fully RNS based ECC Processor

This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over Fp256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.

VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier

In this paper, an area competent field-programmable gate array (FPGA) execution scheme of elliptic curve cryptography (ECC) is depicted. There are numerous limitations in traditional encryption algorithms such us Rivest Shamir Adleman (RSA), Advanced Encryption Standard (AES) in respect of security, power, and resources at the real-time performance. The ECC is mounting as an imperative cryptography, and gives you an idea about a promise to be the substitute of RSA. In this paper, ECC processor architecture over Galois Fields (GFs) with the multitalented bit serial multiplier is depicted which accomplishes the greatest area and power performance over traditional digit-serial multiplier. In addition, the vigilant scheduling operation was employed to diminish the involvedness of logic unit operations in ECC processor. The anticipated architecture is executed on vertex4 FPGA expertise in Xilinx software. We demonstrate that results perk up the performance of the enhanced design by contrasting with the traditional design.

An Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor

Elliptic curve cryptography (ECC) has been widely used for the digital signature to ensure the security in communication. It is important for the ECC processor to support a variety of ECC standards to be compatible with different security applications. Thus, a flexible processor which can support different standards and algorithms is desired. In this paper, an efficient and flexible dual-field ECC processor using the hardware–software approach is presented. The proposed processor can support arbitrary elliptic curve. An elaborate modular arithmetic logic unit is designed. It can perform basic modular arithmetic operations and achieve high efficiency. Based on our designed instruction set, the processor can be programmed to perform various point operations based on different algorithms. To demonstrate the flexibility of our processor, a point multiplication algorithm with power analysis resistance is adopted. Our design is implemented in the field-programmable gate array platform and also in the application-specified integrated circuit. After implemented in the 55 nm CMOS process, the processor takes between 0.60 ms (163 bits ECC) and 6.75 ms (571 bits ECC) to finish one-point multiplication. Compared to other related works, the merits of our ECC processor are the high hardware efficiency and flexibility.

An Energy-Efficient ECC Processor of UHF RFID Tag for Banknote Anti-Counterfeiting

In this paper, we present the design and analysis of an energy-efficient 163-b elliptic curve cryptographic (ECC) processor suitable for passive ultrahigh frequency (UHF) radio frequency identification (RFID) tags that are usable for banknote authentication and anti-counterfeiting. Even partial public key cryptographic functionality has long been thought to consume too much power and to be too slow to be usable in passive UHF RFID systems. Utilizing a low-power design strategy with optimized register file management and an architecture based on the Lopez-Dahab Algorithm, we designed a low-power ECC processor that is used with a modified ECC-DH authentication protocol. The ECC-DH authentication protocol is compatible with the ISO/IEC 18000-63 (“Gen2”) passive UHF RFID protocol. The ECC processor requires 12 145 gate equivalents. The ECC processor consumes 5.04 nJ/b at a frequency of 960 kHz when implemented in a 0.13- $\mu \text{m}$ standard CMOS process. The tag identity authentication function requires 30 600 cycles to complete all scalar multiplication operations. This size, speed, and power of the ECC processor makes it practical to use within a passive UHF RFID tag and achieve up to 1500 banknote authentications per minute, which is sufficient for use in the fastest banknote counting machines.

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).

An Efficient Usage Indian Vedic Shrewdness in Multiplication Module of ECC Co-Processor Architecture

Elliptic Curve Cryptography (ECC) becomes an apparent choice when the security, speed, key length and area constraints are exhorted. This paper implements the ECC over GF(2256) based on the Montgomery scalar multiplication in a field programmable gate array (FPGA) processor with the focus of minimizing the resource binding with random sequence supported by linear feedback shift register (LFSR). Multiplier is most used components of such co-processors and hence even a productive multiplier can save the resource in large extend. This paper employs an efficient multiplier devised from the ancient Indian “Vedic Mathematic Sutras”. The most efficient sutra called “Urdhva Tiryakbhayam” paves a speedy, vertical and crosswise, digital platform supportive and reversible logic implementable multiplier. The proposed ECC processor performs the 256 bit point multiplication with the power consumption of 691mW and utilizes 13918 LUTs for 100 MHz frequency when implemented in a Spartan 3E-XC3S1600E using Modelsim 5.7 and Xilinx 9.2i.

A 5.1μJ per point‐multiplication elliptic curve cryptographic processor

SummarySecurity features such as privacy and device authentication are required in wireless sensor networks, electronic IDs, Radio Frequency Identification tags, and many other applications. These features are provided using cryptography. Symmetric key cryptography, where the key is distributed between the communication parties prior to communication, does not provide adequate solution for large scalable systems such as sensor networks. In these cases, public‐key cryptography should be used. However, public‐key algorithms are typically more computationally intensive than their symmetric key counterparts, which creates difficulties in meeting the strict area, power, and energy requirements. Elliptic curve cryptography, because of relatively small operand sizes, can be used to answer the imposed challenges. In this paper, we present a processor for elliptic curve cryptography over GF(2163). This processor can perform elliptic curve point multiplication as well as general modular operations. The processor is flexible enough to support multiple cryptographic protocols. The chip is fabricated using UMC .13 μm 1P8M process, resulting in a core area of 0.54 mm2. The energy consumption to perform one elliptic curve point multiplication is 5.1 μJ. The design features lightweight countermeasures against side‐channel attacks. A security evaluation shows the effectiveness of such countermeasures. Copyright © 2016 John Wiley & Sons, Ltd.

High‐performance elliptic curve cryptography processor over NIST prime fields

This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high-performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards and Technology standard. A novel combined point doubling and point addition architecture is proposed using efficient modular arithmetic to achieve high speed and low hardware utilisation of the ECP in Jacobian coordinates. This new architecture has been synthesised both in application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA). A 65 nm CMOS ASIC implementation of the proposed ECP in Jacobian coordinates takes between 0.56 and 0.73 ms for 224-bit and 256-bit elliptic curve cryptography, respectively. The ECSM is also implemented in an FPGA and provides a better delay performance than previous designs. The implemented design is area-efficient and this means that it requires not many resources, without any digital signal processing (DSP) slices, on an FPGA. Moreover, the area–delay product of this design is very low compared with similar designs. To the best of the authors’ knowledge, the ECP proposed in this study over F p performs better than available hardware in terms of area and timing.

Parallelization of scalable elliptic curve cryptosystem processors in GF(2m)

The parallelization of scalable elliptic curve cryptography (ECC) processors (ECPs) is investigated in this paper. The proposed scalable ECPs support all 5 pseudo-random curves or all 5 Koblitz curves recommended by the National Institute of Standards and Technology (NIST) without the need to reconfigure the hardware. The proposed ECPs parallelize the finite field arithmetic unit and the elliptic curve point multiplication (ECPM) algorithm to gain performance improvement. The finite field multiplication is separated such that the reduction step is executed in parallel with the next polynomial multiplication. Subsequently, the finite field arithmetic of the ECPs are further parallelized and the performance can be further improved by over 50%. Since the multiplier blocks consume a low number of hardware resources, the latency reduction outweighs the cost of the extra multiplier resulting in more efficient ECP designs. The technique is applied for both pseudo-random curve and Koblitz curve algorithms. A novel ECPM algorithm is also proposed for Koblitz curves that take advantage of the proposed finite field arithmetic architecture. The implementation results show that the proposed parallelized scalable ECPs have better performance compared to state-of-the-art scalable ECPs that support the same set of elliptic curves.

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

A High-Speed FPGA Implementation of an RSD-Based ECC Processor

In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-point multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.

Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves

The architecture and the implementation of a high-performance scalable elliptic curve cryptography processor (ECP) are presented. The proposed ECP is able to support all five prime field elliptic curves recommended by the National Institute of Standards and Technology (NIST). The design takes advantage of the high-performance capabilities of the DSP48E slices available in Xilinx field-programmable gate arrays (FPGAs) to achieve high speed and low hardware resource utilization. The proposed design parallelizes the underlying prime field operations to reduce the latency of the elliptic curve point multiplication (ECPM) operation. Prime field inversion is performed efficiently using the same arithmetic blocks as the ones used for prime field multiplication and addition/subtraction. To the best of the authors' knowledge, the proposed scalable ECP is the fastest and smallest ECP that can support all five NIST recommended prime curves without the need to reconfigure the hardware. It can compute the ECPM between 1.709 and 28.04 ms using a Xilinx Virtex-5 FPGA.