Application Processor Research Articles

A Survey on the Best Choice for Modulus of Residue Code

Nowadays, the development of technology and the growing need for dense and complex chips have led chip industries to increase their attention on the circuit testability. Also, using the electronic chips in certain industries, such as the space industry, makes the design of fault tolerant circuits a challenging issue. Coding is one of the most suitable methods for error detection and correction. The residue code, as one of the best choices for error detection aims, is wildly used in large arithmetic circuits such as multiplier and also finds a wide range of applications in processors and digital filters. The modulus value in this technique directly effect on the area overhead parameter. A large area overhead is one of the most important disadvantages especially for testing the small circuits. The purpose of this paper is to study and investigate the best choice for residue code check base that is used for simple and small circuits such as a simple ripple carry adder. The performances are evaluated by applying stuck-at-faults and transition-faults by simulators. The efficiency is defined based on fault coverage and normalized area overhead. The results show that the modulus 3 with 95% efficiency provided the best result. Residue code with this modulus for checking a ripple carry adder, in comparison with duplex circuit, 30% improves the efficiency.

ML-Assisted DVFS-Aware HEVC Motion Estimation Design Scheme for Mobile APSoC

High-efficiency video coding (HEVC) is the latest video standard, and a variety of HEVC chips are being incorporated into the application processor system-on-a-chip (APSoC) within mobile devices. However, the coding bandwidth accessed for the motion estimation (ME) operation within HEVC has changed over time because of the adoption of the intelligent power management mechanism within the APSoC. To achieve a low-power high-performance HEVC design, the on-demand coding bandwidth must be considered in the design. In this paper, we develop an intelligent dynamic voltage-frequency-scaling-aware (DVFS-aware) coding-bandwidth-efficient HEVC ME controller algorithm model. We also develop a low-power high-performance VLSI hardware architecture by joining a machine learning (ML) scheme and a convex optimization (CO) method that is adaptive to the time-altering coding bandwidth. The proposed HEVC ME controller design can be integrated into ME to realize a coding bandwidth, coding bit rate, and coding-quality-optimized HEVC ME design for mobile APSoC, therein utilizing an intelligent power management mechanism. The experimental results show the effectiveness of the power and performance of the proposed design.

Computational storage: an efficient and scalable platform for big data and HPC applications

In the era of big data applications, the demand for more sophisticated data centers and high-performance data processing mechanisms is increasing drastically. Data are originally stored in storage systems. To process data, application servers need to fetch them from storage devices, which imposes the cost of moving data to the system. This cost has a direct relation with the distance of processing engines from the data. This is the key motivation for the emergence of distributed processing platforms such as Hadoop, which move process closer to data. Computational storage devices (CSDs) push the “move process to data” paradigm to its ultimate boundaries by deploying embedded processing engines inside storage devices to process data. In this paper, we introduce Catalina, an efficient and flexible computational storage platform, that provides a seamless environment to process data in-place. Catalina is the first CSD equipped with a dedicated application processor running a full-fledged operating system that provides filesystem-level data access for the applications. Thus, a vast spectrum of applications can be ported for running on Catalina CSDs. Due to these unique features, to the best of our knowledge, Catalina CSD is the only in-storage processing platform that can be seamlessly deployed in clusters to run distributed applications such as Hadoop MapReduce and HPC applications in-place without any modifications on the underlying distributed processing framework. For the proof of concept, we build a fully functional Catalina prototype and a CSD-equipped platform using 16 Catalina CSDs to run Intel HiBench Hadoop and HPC benchmarks to investigate the benefits of deploying Catalina CSDs in the distributed processing environments. The experimental results show up to 2.2× improvement in performance and 4.3× reduction in energy consumption, respectively, for running Hadoop MapReduce benchmarks. Additionally, thanks to the Neon SIMD engines, the performance and energy efficiency of DFT algorithms are improved up to 5.4× and 8.9×, respectively.

Carbon nanotube covalent bonding mediates extraordinary electron and phonon transports in soft epoxy matrix interface materials

Soft thermal interface materials (TIMs) are essential components for the thermal management of electrical and mechanical devices. However, the low thermal conductivity (κ) still limits efficient heat dissipation. Here we achieve a record high κ (101.7 W m−1 K−1) among soft isotropic TIMs, mediated by the covalent bonding between hydroxyl groups of multiwalled carbon nanotubes (MWNTs) and ester groups of soft epoxy (SE) matrix. It is important to maintain a high relative humidity (60%) during synthesis since the binding reaction is initiated by capturing a proton from environmental moisture. The covalent bonding uniformly distributes MWNTs (0.5 vol%) which construct percolation networks with additional Ag flake fillers (33.5 vol%). The solid electron and phonon contact at the interface is achieved by the coalescence between Ag flakes and Ag nanoparticles pre-functionalized on MWNTs (nAgMWNTs). This dramatically increases electron (11.9 nm) and phonon (105.7 nm) mean free paths and κ. The dispersion of nAgMWNTs is poor without the hydroxyl-ester binding, and the identical filler combination provides very low κ (9.7 and 0.9 W m−1 K−1) in polyurethane and silicone rubber matrices. The κ in SE matrix is 11,300% greater than that in silicone rubber matrix. The soft isotropic nAgMWNT‒Ag flake‒SE TIM shows excellent heat dissipation performance of a cellular phone application processor.

A basic RISC-V verilog datapath project experience for software engineers

Designing processors for special purpose applications such as accelerators is an important skill in the computing community. Broadening the number of students who are exposed to the basic concepts ...

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

This paper demonstrates a signal analysis system-on-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing chain consists of generated instances of a time-interleaved analog-to-digital converter (ADC) followed by a digital tuner, a finite-impulse response (FIR) filter, a polyphase filter, and a fast Fourier transform (FFT) all connected to the five-stage, in-order RISC-V Rocket processor via an AXI4 bus. The generator-based design methodology is detailed, along with the agile design process of producing the fabricated design instance. The $5\,\,\text {mm}\times 5\,\,\text {mm}$ chip is implemented in a 16-nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the application processor and accelerator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art application-specific integrated circuits (ASICs) proves that generators can produce performance-competitive designs.

Effect of Thermoelectric Leg Thickness in a Planar Thin Film TEC Device on Different Substrates

Recently, mobile application processors (APs) have suffered from thermal issues such as local hot spot generation. Several approaches for chip cooling, such as dynamic thermal management, and heat pipe cooling, have been attempted so far, but, these solutions cannot completely eliminate increasing thermal issues. Therefore, in this study, we fabricated a planar type of thin film thermoelectric cooler (TEC) as an active cooling device for a mobile AP chip. We studied the effect of thickness on a planar thin film TEC device related to Joule heating and demonstrated the Peltier cooling effect on polyimide (PI) and Si substrates. The optimal thicknesses of n-type Bi2Te3 and p-type Sb2Te3 films were evaluated by ANSYS® simulation, and are 5.05 μm and 5.45 μm, respectively. It was shown that heat moves to the TE leg on the PI substrate, while the Si substrate serves as a heat sink according to the IR thermography analysis. The optimal thickness of the TE showed a temperature difference between the cold junction and hot junction up to 1.3 °C.

Production of Hydrogen-Rich Gas by Formic Acid Decomposition over CuO-CeO2/γ-Al2O3 Catalyst

Formic acid decomposition to H2-rich gas was investigated over a CuO-CeO2/γ-Al2O3 catalyst. The catalyst was characterized by XRD, HR TEM and EDX methods. A 100% conversion of formic acid was observed over the copper-ceria catalyst under ambient pressure, at 200–300 °C, N2:HCOOH = 75:25 vol.% and flow rate 3500–35,000 h−1 with H2 yield of 98%, wherein outlet CO concentration is below the equilibrium data (<0.5 vol.%). The copper-ceria catalyst proved to be promising for multifuel processor application, and the H2 generation from dimethoxymethane, methanol, dimethyl ether and formic acid on the same catalyst for fuel cell supply.

(Invited) Enabling Fan-out Wafer-Level Package (FOWLP) through Innovative Copper Electrodeposition Processes

IC packaging technology has evolved in a quite diverse manner over the past decade, addressing both high-end and low-end applications, resulting in approaches such as package-on-package (PoP), fan-out wafer-level package (FOWLP), 3D IC integration with through-silicon via (TSV), and 2.5D with TSV-Si interposer. FOWLP technology offers significant cost and performance advantages relative to other packaging approaches and is therefore receiving widespread adoption throughout the industry for applications such baseband processor and applications processor (AP). It is anticipated that this technology may be extended for high-end devices such as field-programmable gate array (FPGA) and graphics processing unit (GPU). As a result, FOWLP technology is expected to ramp at a strong growth rate over the immediate future. FOWLP technology comprises conventional under-bump metallization (UBM) and pillar/micro-pillar, as well as new routing/connection applications such as fine-line redistribution layer (RDL) (sub 5x5 mm), integrated via-RDL structures, and mega pillars (>150 mm). These new applications drive fundamental challenges in electrodeposition. Fine-line RDL applications present challenges for both lithography and electrochemical deposition (ECD) processes. For wafer handling, the reconstituted wafers used in FOWLP can exhibit significant warpage and maintaining feature dimensions across wafer topography becomes challenging. New electroplating technology is required to prevent physical degradation of the fine-line RDL. Etchants used for copper (Cu) wet etch will preferentially attack the interface between the Cu ECD line and the Cu physical vapor deposition (PVD) seed layer, resulting in an undercut that degrades the mechanical reliability. This undercut can be minimized by using innovative electroplating technology to reduce the thickness of the Cu PVD seed layer. Thermal cracking of the Cu line has also been posed as a key integration challenge. Grain engineering is discussed as one potential solution to overcome this issue. Many of the current FOWLP approaches include the adoption of multi-layer RDL which are fabricated from low dielectric polymer passivation layers and Cu ECD lines. Multi-layer RDL patterns can result in significant topography variation, which can impact other process integration challenges such as control of critical dimensions (CDs). To minimize topography variation, a new ECD reactor design is used to provide ultra-uniform Cu ECD. Mega pillars consist of 180-220 mm (200 mm average) Cu thickness while standard Cu pillar applications typically vary between 20 and 40 μm (30 mm average) thickness. This large disparity in thickness can translate to approximately 6x longer plating times if a similar deposition rate is used. The process of plating large features employed as interconnects often encounters mass transport limitations that can curtail the deposition rate. This effect is explored in detail via computational modeling. The aspect ratio of through-resist features is shown to have a severe impact on minimum fill time, where a high (4:1) aspect ratio feature takes more than 7.5 times as long to fill as a low (1.2:1) aspect ratio feature. Convection of the electrolyte above the surface of the photoresist, which is largely influenced by the ECD reactor design, is shown to have a pronounced impact on fill times over the range of feature dimensions. Furthermore, some integration requirements for mega pillars warrant extremely high within-die uniformities and flat bump shape. Attaining such high-quality plating performance can greatly minimize the downstream planarization requirements. This paper will focus on new innovations in Cu ECD processes for fine line RDL, multi-layer RDL, and mega pillar to enable FOWLP technology.

Design of Low Power and High Speed 4X4 Multiplier using Modified Column Bypassing Scheme for DSP Applications

In this paper a low power and high speed 4X4 multiplier is designed using CMOS Technology. The important factors in VLSI Design are power, area, speed and design time. Now-a-days, power and speed has become a crucial factor in Digital Signal Processor (DSP) Applications. However, different optimization techniques are available in the digital electronic world. The proposed approach a Low power and high speed Multiplier Design based on Modified Column bypassing technique mainly used to reduce the switching power activity. While this technique offers great dynamic power savings, due to their interconnection. In this work, a low power and high speed multiplier with Hybridization scheme is presented. This scheme is combination of booth encoder algorithm and column bypass technique is called modified column bypassing scheme. The simulations are performed in 0.18µm CMOS Technology in Cadence Virtuoso tools with operating voltage ±1.8v

To implement positive feedback adiabatic logic (PFAL)—NAND technique on low power Zigbee applications for processor applications

In recent years, field of Microprocessor and system world, where Zigbee is one of most important device for collect and transmitting the information from patient body and particular place to remote stations with efficient way. Power consumption is most important one for wireless devices. In present, most of the wireless devices are designed and developed by various design methodologies. Where logical system is complex for designing the wireless devices. In this paper, we propose a novel method of positive feedback adiabatic logic (PFAL) NAND technique for low power Zigbee applications for processor field. Here to implement positive feedback adiabatic logic – NAND technique on low power Zigbee applications is to be proposed. It employs the concept of adiabatic charge recovery. The circuit design has the less power consumption for the application of Zigbee low power mode this become critical concern. The adiabatic logic refers to a system in which a transition may occur without energy that is in the form of heat. It is the low power circuits which help to use reversible logic to conserve energy. The adiabatic circuits are operating on the principle of adiabatic charging and discharging process. It is to be used for partial energy recovery circuit and it has the lowest energy consumption which is compared to similar relatives. It is the best robustness which is against technological parameter variations.

A Thermal Mitigation Algorithm Based on the Power Characteristics of Mobile Application Processors

Modern mobile devices suffer from severe power and thermal issues due to the adoption of high-frequency multi-core processors. However, methods of resolving the thermal problems in mobile environments are restricted due to their size, semiconductor process technology, and battery limitations. Mobile devices generally rely on a software framework called the Thermal Management Model (TMM). However, conventional TMMs suffer from inevitable performance degradation due to the thermal response. We propose a new Thermal Mitigation Algorithm (TMA) to optimize performance and thermal mitigation by considering the multi-core power curve of a mobile CPU which is experimentally derived using a typical smartphone and thus resolve this issue. Our proposed scheme aims to reduce thermal problems and enhance system performance by limiting the usage of power-inefficient frequencies when operating on a multi-core. We evaluate the proposed algorithm on a real system using a typical smartphone and conduct the performance measurement using the AnTuTu benchmark v4.5.1. In addition, we use the on-chip temperature sensors of CPU cores and a crystal oscillator embedded in the Application Processor (AP) to monitor the temperature of the mobile device. The result shows that our scheme, respectively reduce the average temperatures of CPU cores and a crystal oscillator by 6.61% and 5.02% while improving system performance by 3.24%. In conclusion, we reduce the thermal problems and enhance performance simultaneously using the proposed TMA.

A 25-MHz Four-Phase SAW Hysteretic Control DC–DC Converter With 1-Cycle Active Phase Count

In order to meet stringent power requirements in modern application processors, a 25-MHz four-phase dc–dc power converter is presented. It employs an adaptive window hysteretic control to facilitate ultra-fast transient response and minimize output voltage ( $V_{O}$ ) undershoot and overshoot during load transient periods. Inherent clock synchronization ability ensures current balancing between phase sub-converters. The control also enables a wide range of programmable $V_{O}$ for dynamic voltage/frequency scaling. To maintain high efficiency over a wide power range without degrading transient speed, a 1-cycle active phase count scheme is introduced. A design prototype was fabricated in a 0.35- $\mu \text{m}$ CMOS process with an active die of 1.88 mm2. Simple circuit structure benefits a power density of 3.98 W/mm2. At a switching frequency of 25 MHz and a nominal input of 3.3 V, it regulates a programmable $V_{O}$ ranging from 0.3 to 2.5 V. It achieves more than 80% efficiency over 96.7% of power range with a peak value of 88.1%. In response to 4-A load step-up/down, it achieves 103 mV/123 mV $V_{O}$ undershoot/overshoot with 1% settling time of 190 ns/237 ns, respectively.

Design and Implementation of a New Wireless Carotid Neckband Doppler System with Wearable Ultrasound Sensors: Preliminary Results

Noninvasive monitoring of blood flow in the carotid artery is important for evaluating not only cerebrovascular but also cardiovascular diseases. In this paper, a wireless neckband ultrasound Doppler system, in which two 2.5-MHz ultrasonic sensors are utilized for acquiring Doppler signals from both carotid arteries, is presented for continuously evaluating blood flow dynamics. In the developed wireless neckband Doppler system, the acquired Doppler signals are quantized by 14-bit analog-to-digital-converters running at 40 MHz, and pre-processing operations (i.e., demodulation and clutter filtering) are performed in an embedded field programmable gate array chip. Then, these data are transferred to an external smartphone (i.e., Galaxy S7, Samsung Electronics Co., Suwon, Korea) via Bluetooth 2.0. Post-processing (i.e., Fourier transform and image processing) is performed using an embedded application processor in the smartphone. The developed carotid neckband Doppler system was evaluated with phantom and in vivo studies. In a phantom study, the neckband Doppler system showed comparable results with a commercial ultrasound machine in terms of peak systolic velocity and resistive index, i.e., 131.49 ± 3.97 and 0.75 ± 0.02 vs. 131.89 ± 2.06 and 0.74 ± 0.02, respectively. In addition, in the in vivo study, the neckband Doppler system successfully demonstrated its capability to continuously evaluate hemodynamics in both common carotid arteries. These results indicate that the developed wireless neckband Doppler system can be used for continuous monitoring of blood flow dynamics in the common carotid arteries in point-of-care settings.

Design of Eight Parallel 512-Point MDF FFT/IFFT Processor for WPAN Applications

This paper presents a high-speed FFT algorithm for high data rate wireless personal area network applications. In a wireless personal area network, the FFT/IFFT block leads the major role. Computational requirements of FFT processors are a heavy burden in most real-time applications. From the previous work, it can be recognized that most of the FFT structures follow the divide and conquer algorithms, which improve the computational efficiency. In the proposed model, a new design of 512-point FFT/IFFT processor is derived by mixed approach for a Radix-26 algorithm, which has been presented and implemented using the Eight Parallel Multipath Delay Feedback (MDF) architecture. In this work, three distinct complex multiplication approaches are derived; from the analysis, a mixed approach has been proposed to reduce the multiplier complexity and also the equivalent normalized area. The proposed design is compiled and simulated with 90[Formula: see text]nm CMOS technology optimized for a 1.2[Formula: see text]V supply voltage. The proposed Mixed Radix-26 algorithm has been verified and validated using existing architectures. It has been found that the proposed mixed approach for Radix-26 algorithm reduces the normalized area by 8.603% compared with verified architectures. Also, the multiplier complexity is reduced by more than 33% using Canonical Signed Digit constant multiplier. The proposed architecture is suitable for applications like OFDM based WPAN applications at high data processing rates.

SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications

We here present a new PLC-POWERLINK industrial solution for Industry 4.0 applications. The proposed solution provides the capability to separate the sensing functionality from the PLC-side, in demand for the reconfigurable FPGA implementation. In particular, we here provide a framework that supports the interfacing between the POWERLINK protocol and commonly used standards, such as I2C, SPI, and UART. This has been obtained by using a framework built around a soft IP-core Application Processor, which manages the interfacing with several POWERLINK slaves, able to support the data exchange with the POWERLINK Communication Processor. A practical application example and related implementation details are presented in the paper.

Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors

Presently, leakage in a complementary metal oxide semiconductor (CMOS) increases due to high static power dissipation during reading and writing operations. Spin transfer torque magnetic random access memory is seen as the most reassuring non-volatile memory structure to overcome the current problem of static power dissipation. In conventional techniques, magnetic flip-flop (MFF) consumes large power and static current dissipation due to conditional-based single circuitry, which can be optimized through introduction of MFF with the combination of low swing conditional capture edge-trigged flip-flop, self-time logical writing circuit, and coarse-grain-based power gating circuit. This method has been developed particularly for high-precision, high-speed, mixed-mode application-specific integrated circuits; the reduction in total power consumption, static current, and PDP shows the proposed technique that as highly suitable for low power applications in high-end processors, using nanoscale technology. In this research work, results have been validated by simulations and measurements using 180 nm CMOS technology, tested using 1.8 v supply voltage.

Asynchronous Event-Based Motion Processing: From Visual Events to Probabilistic Sensory Representation.

In this work, we propose a two-layered descriptive model for motion processing from retina to the cortex, with an event-based input from the asynchronous time-based image sensor (ATIS) camera. Spatial and spatiotemporal filtering of visual scenes by motion energy detectors has been implemented in two steps in a simple layer of a lateral geniculate nucleus model and a set of three-dimensional Gabor kernels, eventually forming a probabilistic population response. The high temporal resolution of independent and asynchronous local sensory pixels from the ATIS provides a realistic stimulation to study biological motion processing, as well as developing bio-inspired motion processors for computer vision applications. Our study combines two significant theories in neuroscience: event-based stimulation and probabilistic sensory representation. We have modeled how this might be done at the vision level, as well as suggesting this framework as a generic computational principle among different sensory modalities.

Demystifying Arm TrustZone

The world is undergoing an unprecedented technological transformation, evolving into a state where ubiquitous Internet-enabled “things” will be able to generate and share large amounts of security- and privacy-sensitive data. To cope with the security threats that are thus foreseeable, system designers can find in Arm TrustZone hardware technology a most valuable resource. TrustZone is a System-on-Chip and CPU system-wide security solution, available on today’s Arm application processors and present in the new generation Arm microcontrollers, which are expected to dominate the market of smart “things.” Although this technology has remained relatively underground since its inception in 2004, over the past years, numerous initiatives have significantly advanced the state of the art involving Arm TrustZone. Motivated by this revival of interest, this paper presents an in-depth study of TrustZone technology. We provide a comprehensive survey of relevant work from academia and industry, presenting existing systems into two main areas, namely, Trusted Execution Environments and hardware-assisted virtualization. Furthermore, we analyze the most relevant weaknesses of existing systems and propose new research directions within the realm of tiniest devices and the Internet of Things, which we believe to have potential to yield high-impact contributions in the future.

Towards design and automation of a scalable split-radix FFT processor for high throughput applications

Fast Fourier Transform (FFT) is a rudimentary operation in signal processing. Modern high speed signal processing and communications standards, such as 4G LTE, 5G, Internet of Things (IoT), etc., necessitate a high throughput implementation of FFT. Moreover the FFT resolution required in aforementioned standards tends to vary with the operation mode. It is, therefore, highly desirable to have a FFT implementation that not only meets the high throughput demand but is also scalable to cater any selectable N-point FFT resolution. In this paper, our contribution is two-fold. First, we have analyzed in details the operational latency and mathematical consistency of our proposed split-radix 4/8 FFT algorithm which is comparable in latency with radix-8 algorithm but is considerably less complex for large-size FFTs. Second, we have developed a JAVA-based automation tool that generates high level implementation details and VHDL descriptions of an adaptive N-point split-radix 4/8 FFT processor. The resulting design can then be rapidly prototyped and synthesized on different hardware platforms like Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Experimental results show that our proposed auto-generated modular design is comparable in resource usage with the hand-crafted fixed-size designs reported in the literature while providing considerable reduction in design effort and time.