Processor Failures Research Articles

Incremental compiler transformations for multiple instruction retry

AbstractPrevious work on compiler‐based multiple instruction retry has utilized a series of compiler transformations, loop protection, node splitting, and loop expansion, to eliminate anti‐dependencies of length ≤ N in the pseudo register, the machine register, and the post‐pass resolver phases of compilation.1 The results have provided a means of rapidly recovering from transient processor failures by rolling back N instructions. This paper presents techniques for improving compilation and run‐time performance in compiler‐based multiple instruction retry. Incremental updating enhances compilation time when new instructions are added to the program. Post‐pass code rescheduling and spill register reassignment algorithms improve the run‐time performance and decrease the code growth across the application programs studied. Branch hazards are shown to be resolvable by simple modifications to the incremental updating schemes during the pseudo register phase and to the spill register reassignment algorithm during the post‐pass phase.

Testing of programmable analog neural network chips

Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.

Efficient algorithms for optimistic crash recovery

Recovery from transient processor failures can be achieved by using optimistic message logging and checkpointing. The faulty processors roll back, and some/all of the non-faulty processors also may have to roll back. This paper formulates the rollback problem as a closure problem. A centralized closure algorithm is presented together with two efficient distributed implementations. Several related problems are also considered and distributed algorithms are presented for solving them.

The distributed voting strategy for fault diagnosis and reconfiguration of linear processor arrays

Abstract A new strategy for fault diagnosis and reconfiguration of linear processor arrays is proposed. This strategy can be implemented in a distributed manner, suitable for arrays with a large number of processors such as those implemented by VLSI and WSI techniques. The proposed fault diagnosis is based on the distributed voting technique. Additional links are added for fault diagnosis. These links are also used, when there is a processor failure, for communication between the processors. Some reconfiguration schemes are also presented emphasizing the distributed approach.

Distributed algorithms with random processor failures

Examines a distributed algorithm where the processors may fail in a random fashion. This results in a model with random communication delays. Convergence conditions are derived. Extensions of the analysis and results to cases where the random processor failures are perceived and corrected within random time intervals are possible. For the sake of simplicity, the analysis is presented for a two processor model for solving a system of linear equations. >

Optimistic crash recovery without rolling back nonfaulty processors

The problem of recovering from transient processor failures in distributed computing systems using optimistic message logging is considered, and two crash recovery algorithms are presented. Both algorithms have three advantages: 1. (1) no nonfaulty processor is forced to roll back 2. (2) output messages may be committed immediately, and 3. (3) a nonfaulty processor is not disrupted if none of its neighbors is faulty. The first algorithm uses acknowledgments, permits at most two neighboring processors to fail at the same time, and does not block the receiver or the sender of each message. The second algorithm copes with the simultaneous failure of any number of nodes, but it requires that the sender id of each message (not its content) be logged to stable storage before the message is processed. Though the second algorithm blocks the receiver, the blocking time can be substantially reduced. In both cases, the state of a faulty processor immediately before its failure is recreated. Thus, after either of the two crash recovery algorithms is run, the distributed system restarts from a consistent state.

Scheduling hard real-time tasks with tolerance of multiple processor failures

Real-time systems are used extensively in applications that are mission-critical and life-critical, such as space exploration, aircraft avionics, and robotics. Since these systems are usually operating in environments that are non-deterministic, and even hazardous, it is extremely important that hard deadlines of tasks be met even in the presence of certain failures. To tolerate processor failures, the problem of scheduling a set of real-time tasks with duplication is studied. We first prove that the problem of scheduling a set of non-preemptive tasks on m ≥ 3 processors to tolerate one arbitrary processor is NP-complete even when the tasks share a common deadline. A heuristic algorithm is then proposed to solve the problem. The schedule generated by the algorithm can tolerate, in the worst case, one arbitrary processor failure, but in the best case [ m/2] processor failures, where m is the number of processors. Experimental data and analysis show that the performance of the algorithm is near-optimal.

Fast fault-tolerant digital convolution using a polynomial residue number system

A fault-tolerant convolution algorithm that is an extension of residue-number-system fault-tolerance schemes applied to polynomial rings is described. The algorithm is suitable for implementation on multiprocessor systems and is able to concurrently mask processor failures. A fast algorithm based on long division for detecting and correcting multiple processor failures is presented. Moduli polynomials that yield an efficient and robust fast-Fourier transform (FFT)-based algorithm are selected. For this implementation, a single fault detection and correction is studied, and a generalized-likelihood-ratio test is applied to optimally detect system failures in the presence of computational noise. The coding scheme is capable of protecting over 90% of the computation involved in convolution. Parts not covered by the scheme are assumed to be protected via triple modular redundancy. This hybrid approach can detect and correct any single system failure with as little as 70% overhead, compared with 200% needed for a system fully protected via modular redundancy. >

Generalized measures of fault tolerance in n-cube networks

It is shown that for a given p (1<p<or=n), the n-cube network can tolerate up to p2/sup (n-p)/-1 processor failures and remains connected provided that at most p neighbors of any nonfaulty processor are allowed to fail. This generalizes the result for p=n-1, obtained by A.-M Esfahanian (1989). It is also shown that the n-cube network with n>or=5 remains connected provided that at most two neighbors of any processor are allowed to fail.<<ETX>>

Common knowledge and consistent simultaneous coordination

There is a very close relationship between common knowledge and simultaneity in synchronous distributed systems. The analysis of several well-known problems in terms of common knowledge has led to round-optimal protocols for these problems, including Reliable Broadcast, Distributed Consensus, and the Distributed Firing Squad problem. These problems require that the correct processors coordinate their actions in some way but place no restrictions on the behaviour of the faulty processors. In systems with benign processor failures, however, it is reasonable to require that the actions of a faulty processor be consistent with those of the correct processors, assuming it performs any action at all. We consider problems requiring consistent, simultaneous coordination. We then analyze these problems in terms of common knowledge in several failure models. The analysis of these stronger problems requires a stronger definition of common knowledge, and we study the relationship between these two definitions. In many cases, the two definitions are actually equivalent, and simple modifications of previous solutions yield round-optimal solutions to these problems. When the definitions differ, however, we show that such problems cannot be solved, even in failure-free executions.

FLIP: an internetwork protocol for supporting distributed systems

Most modern network protocols give adequate support for traditional applications such as file transfer and remote login. Distributed applications, however, have different requirements (e.g., efficient at-most-once remote procedure call even in the face of processor failures). Instead of using ad hoc protocols to meet each of the new requirements, we have designed a new protocol, called the Fast Local Internet Protocol (FLIP), that provides a clean and simple integrated approach to these new requirements. FLIP is an unreliable message protocol that provides both point-to-point communication and multicast communication, and requires almost no network management. Furthermore, by using FLIP we have simplified higher-level protocols such as remote procedure call and group communication, and enhanced support for process migration and security. A prototype implementation of FLIP has been built as part of the new kernel for the Amoeba distributed operating system, and is in daily use. Measurements of its performance are presented.

Connection establishment in high-speed networks

Protocols for establishing, maintaining, and terminating connections in packet-switched networks have been studied, and numerous standards have been developed to address this problem. The authors reexamine connection establishment in the context of a high-speed packet network, introduce a protocol for connection establishment/takedown that is appropriate for such a network, and explain its advantages over previously proposed protocols. The main features of the proposed protocol are: fast bandwidth reservation in order to avoid as much as possible reservation conflicts, guaranteed release of the reserved bandwidth even under modal and link failures, and soft recovery from processor failures, which allows the maintenance of existing connections under processor failure provided the switch and links do not fail. The underlying model that is used is the PARIS/plaNET network, but the protocol can be adapted to other fast packet networking architectures as well. >

A performance study of three high availability data replication strategies

The paper studies the relative performance of chained declustering, mirrored disks, and interleaved declustering, in a shared nothing database machine environment. In particular, it examines the relative performance of the three strategies when no failures have occurred, the effect of load imbalance caused by a disk or processor failure on system throughput and response time, and the tradeoff between the benefit of intra query parallelism and process scheduling overhead. >

Combinatorial analysis of the fault-diameter of the n-cube

It is shown that the diameter of an n-dimensional hypercube can only increase by an additive constant of 1 when (n-1) faulty processors are present. Based on the concept of forbidden faulty sets, which guarantees the connectivity of the cube in the presence of up to (2n-3) faulty processors. It is shown that the diameter of the n-cube increases to (n-2) as a result of (2n-3) processor failures. It is also shown that only those nodes whose Hamming distance is (n-2) have the potential to be located at two ends of the diameter of the damaged cube. It is proven that all the n-cubes with (2n-3) faulty processors and a fault-diameter of (n+2) are isomorphic. A generalization to the subject study is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Failure rates for programmable logic controllers

Abstract Programmable logic controllers (PLCs) are used in many industrial control and/or safety applications. The increased use of quantitative reliability analysis, particularly in the chemical process and nuclear industries, requires additional and more detailed failure rate estimates for analyzing PLCs. This technical note presents failure rates derived from actual PLC performance in chemical process and nuclear power plants. Failure rate estimates range from 0·0082/year to 0·025/year. These values are remarkably consistent when one considers that the data analyzed come from PLCs from different manufacturers, of different size and complexity, and with different control/safety uses. Coverage values, the probability that a PLC with redundant processors will recover from a single processor failure by successfully switching the control function(s) to the other processor, derived in this study range from 98·37% to 99·59%.

Fault diagnosis for the generalized Boolean n-cube network

In this paper the fault-tolerant characteristics of the generalized Boolean n-cube network are studied. For processor failures the network is shown to be n+1 (one step) diagnosable. Two efficient algorithms which can diagnose up to n+1 processor failures are presented and their computational complexity are studied.

Chordal rings as fault-tolerant loops

The loop is a commonly used interconnection network for computer systems. In this paper we consider the problem of making a loop network fault-tolerant. Previous solutions employ the absolute minimum number of redundant components, for a specified level of fault-tolerance. In our approach, “extra” redundancy is used to reduce the size and complexity of the interconnection network. Designs based on chordal rings are presented which can tolerate one and two processor failures. The examples given indicate that for large scale systems, the approach can produce improvement over previous approaches, yielding designs which are more in accord with the limitations of current technology.

Analysis of a fault-tolerance scheme for processor ensembles

The authors analyze a locally redundant scheme (LR scheme) for designing fault-tolerant processor ensembles. A switching structure for reconfiguration is presented, and a detailed model for the yield analysis off the LR scheme that takes into account processor, switch, and link failures is developed. A negative binomial distribution is used for the yield statistics, as it best fits the empirical data. This model is used to compare the yields (with and without fault tolerance) of some architectural topologies. A dynamic analysis of the effect of residual redundancy on the improvement of operational system reliability is presented. The analysis reveals an appreciable improvement in the yield and operational system-reliability when the LR scheme is used. This analysis includes the reliability of switches and links, unlike previous analyses of fault-tolerant schemes. The empirical results show that ignoring switch reliability could result in an appreciable overestimate of system reliability. >

Optimal agreement protocol in malicious faulty processors and faulty links

Traditionally, the problems of Byzantine agreement, consensus, and interactive consistency are studied in a fully connected network with processors in malicious failure only. Such problems are reexamined with the assumption of malicious faults on both processors and links. The proposed protocols use the minimum number of message exchanges and can tolerate the maximum number of allowable faulty components to make each fault-free processor reach a common agreement for the cases of processor failure, link failure, or processor and link failure. >

Efficient parallel algorithms can be made robust

The efficient parallel algorithms proposed for many fundamental problems, such as list ranking, integer sorting and computing preorder numberings on trees, are very sensitive to processor failures. The requirement of efficiency (commonly formalized using Parallel-time × Processors as a cost measure) has led to the design of highly tuned PRAM algorithms which, given the additional constraint of simple processor failures, unfortunately become inefficient or even incorrect. We propose a new notion of robustness, that combines efficiency with fault tolerance. For the common case of fail-stop errors, we develop a general and easy to implement technique to make robust many efficient parallel algorithms, e.g., algorithms for all the problems listed above. More specifically, for any dynamic pattern of fail-stop errors on a CRCW PRAM with at least one surviving, processor, our method increases the original algorithm cost by at most a log2 multiplicative factor. Our technique is based on a robust solution of the problem of Write-All, i.e., using P processors, write 1's in all locations of an N-sized array. In addition we show that at least a log/log log multiplicative overhead will be incurred for certain patterns of failures by any algorithm that implements robust solutions to Write-All with P = N. However, by exploiting parallel slackness, we obtain an optimal cost algorithm when P ≤ N/log2N-logNloglogN.