Processor Efficiency Research Articles

On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches

When hardware cache coherence scales to many cores on chip, over saturated traffic of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update protocol in terms of on-chip memory network traffic and its adverse effects on the system performance based on a multithreaded many-core architecture with distributed caches. We discuss possible software and hardware solutions to alleviate the network pressure. We find that in the context of massive concurrency, by introducing a write-merging buffer with 0.46% area overhead to each core, applications with good locality and concurrency are boosted up by 18.74% in performance on average. Other applications also benefit from this addition and even achieve a throughput increase of 5.93%. In addition, this improvement indicates that higher levels of concurrency per core can be exploited without impacting performance, thus tolerating latency better and giving higher processor efficiencies compared to other solutions.

Customized pipeline and instruction set architecture for embedded processing engines

Custom instructions potentially improve execution speed and code compression of embedded applications. However, more efficient custom instructions need higher number of simultaneous registerfile accesses. Larger registerfiles are more power hungry with complex forwarding interconnects. Therefore, due to the limited ports of the base processor registerfile, size and efficiency of custom instructions could be generally limited. Recent researches have focused on overcoming this limitation by some innovative architectural techniques supplemented with customized compilations. However, to the best of our knowledge there are few researches that take into account the complete pipeline design and implementation considerations. This paper proposes a customized instruction set and pipeline architecture for an optimized embedded engine. The proposed architecture increases the performance by enhancing the available registerfile data bandwidth through register access pipelining. The achieved improvements are made by introducing double-word custom instructions whose registerfile accesses are overlapped in the pipeline. Potential hazards in such instructions are resolved by the introduced pipeline backwarding concept, yielding higher performance and code compression. While we study the effectiveness of the proposed architecture on domain-specific workloads from packet-processing benchmarks, the developed framework and architecture are applicable to other embedded application domains.

매니코어 프로세서를 이용한 SIFT 알고리즘 병렬구현 및 성능분석

본 논문에서는 대표적인 특징점 추출 알고리즘인 SIFT(Scale-Invariant Feature Transform)를 매니코어 프로세서를 이용하여 병렬 구현하고, 이를 실행 시간, 시스템 이용률, 에너지 효율 및 시스템 면적 효율 측면에서 분석하였다. 또한 기존의 고성능 CPU와 GPU(Graphics Processing Unit)와의 성능 비교를 통해 제안하는 매니코어의 잠재가능성을 입증하였다. 모의실험 결과, 매니코어를 이용한 SIFT 알고리즘 구현 결과는 기존의 OpenCV 구현 결과와 정확도면에서 동일하였고, 매니코어 구현은 고성능 CPU 및 GPU 구현보다 실행시간 측면에서 우수하였다. 또한 본 논문에서는 SIFT알고리즘의 옥타브 크기에 따른 에너지 효율 및 시스템 면적 효율을 분석하여 최적의 모델을 제시하였다. In this paper, we implement the SIFT(Scale-Invariant Feature Transform) algorithm for feature point extraction using a many-core processor, and analyze the performance, area efficiency, and system area efficiency of the many-core processor. In addition, we demonstrate the potential of the proposed many-core processor by comparing the performance of the many-core processor with that of high-performance CPU and GPU(Graphics Processing Unit). Experimental results indicate that the accuracy result of the SIFT algorithm using the many-core processor was same as that of OpenCV. In addition, the many-core processor outperforms CPU and GPU in terms of execution time. Moreover, this paper proposed an optimal model of the SIFT algorithm on the many-core processor by analyzing energy efficiency and area efficiency for different octave sizes.

Measuring Processor Frequency for Load Stability in Multi-Core MIMD Architecture

Parallelism, a massive achievement in the field of processor architecture leading towards increased speed up by incorporating data as well as computation intensive work. Parallel architectural components interconnected with major consideration as communication among coupled hardware in order to stabilize workload distribution and management. Workload distribution with load stability fundamentally a tricky aspect of parallel distribution. Static policies covers load factors which are pre-determined before actually distribution takes place. Dynamic load stability and distribution periodically measures the load for each and every processor in heterogenic parallel processor systems.. Development of heterogenic multiprocessor machines with dynamic load stability matrices or measurements incorporates vast amount of efforts and covers varied amount of configuration factors on the behalf of the underlying communication architecture. So much of the processor’s efforts may lose for load stabilization, which may be controlled by improved dynamic load stability techniques and theories. In this research, the major aspect of development is to measure processor efficiency by analyzing frequency speed along with current processor load, only then the distribution takes place. Measuring cycle speed (i.e. no. of cycle per second elapsed) in terms of Hz, Mhz, Ghz is one of the measurement metric to analyze the processor efficiency. Further the research covers MIMD based core processor simulation version integrate frequency based distribution for load steadiness and control. Although, load consistency will not be completely managed with in any type of system. Load steadiness and uniformity will only be controlled up to some extent. General Terms Dynamic Job scheduling, Load Balancing and consistency, Processor Efficiency, Multi-Core MIMD Systems, Cycle Speed.

Hydrogen production by onboard gasoline processing – Process simulation and optimization

Fuel cell vehicles have reached the commercialization stage and hybrid vehicles are already on the road. While hydrogen storage and infrastructure remain critical issues in stand alone commercialization of the technology, researchers are developing onboard fuel processors, which can convert a variety of fuels into hydrogen to power these fuel cell vehicles. The feasibility study of a 100kW on board fuel processor based on gasoline fuel is carried out using process simulation. The steady state model has been developed with the help of Aspen HYSYS to analyze the fuel processor and total system performance. The components of the fuel processor are the fuel reforming unit, CO clean-up unit and auxiliary units. Optimization studies were carried out by analyzing the influence of various operating parameters such as oxygen to carbon ratio, steam to carbon ratio, temperature and pressure on the process equipments. From the steady state model optimization using Aspen HYSYS, an optimized reaction composition in terms of hydrogen production and carbon monoxide concentration corresponds to: oxygen to carbon ratio of 0.5 and steam to carbon ratio of 0.5. The fuel processor efficiency of 95.98% is obtained under these optimized conditions. The heat integration of the system using the composite curve, grand composite curve and utility composite curve were studied for the system. The most appropriate heat exchanger network from the generated ones was chosen and that was incorporated into the optimized flow sheet of the100kW fuel processor. A completely heat integrated 100kW fuel processor flow sheet using gasoline as fuel was thus successfully simulated and optimized.

Improving processor efficiency by statically pipelining instructions

A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.

Validated Real Time Middle Ware For Distributed Cyber Physical Systems Using Hmm

Distributed Cyber Physical Systems designed for different scenario must be capable enough to perform in an efficient manner in every situation. E arlier approaches, such as CORBA, has performed but with different time constraints. Therefore, there was the need to design reconfigurable, robust, validated and consistent real time middle ware systems with end -to-end timing. In the DCPS-HMM we have proposed the processor efficiency and data validation which may proof crucial in implementing various distributed systems such as credit card systems o r file transfer through network.

Current Studies On Intrusion Detection System, Genetic Algorithm And Fuzzy Logic

Distributed Cyber Physical Systems designed for different scenario must be capable enough to perform in an efficient manner in every situation. Earlier approaches, such as CORBA, has performed but with different time constraints. Therefore, there was the need to design reconfigurable, robust, validated and consistent real time middle ware systems with end-to-end timing. In the DCPS-HMM we have proposed the processor efficiency and data validation which may proof crucial in implementing various distributed systems such as credit card systems or file transfer through network.

A Cryptographic Processor for 32 bit Embedded System with Resource-Constraints

With the information breaches growing nowadays, the demand for serious efforts towards ensuring security in embedded systems becomes more important. The successful employment of these embedded systems for e-commerce, transaction banking, mobile commerce, etc, depend on the reliability of the security solutions. Respecting the real-time performance and the resource-constrained target environment for the next-generation applications, the embedded system design have been a theme of serious study these last few years. This paper presents a hardware crypto-processor for the arising issue of information security in embedded system. This crypto-processor can be used for various security applications such as smartcards, network routers, wireless systems, etc. The proposed 32-bit processor executes various IP crypto cores like hash function, private and public key operations, Random Number generator and other application programs such as user authentication. The hardware description is done in ModelSim using VHDL and synthesized using Synopsys Design Compiler. Furthermore, the proposed crypto-processor is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40 nm technology. The results show a high performance, confirming the efficiency of the processor. We have carefully chosen the dedicated algorithms to reduce the required memory resources while respecting the necessary runtime within reasonable limits. The proposed crypto-processor has a total core area of 1.35 mm2 and can achieve an operating system frequency of 500 MHz. The estimated power of the chip was 4,6 mW at 10 MHz.

Towards energy-proportional datacenter memory with mobile DRAM

To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3x the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5x lower memory power, better proportionality, and negligible performance penalties for datacenter workloads.

Productivity of Timber Processing in Ondo State, Nigeria

<p>This study is aimed at evaluating the efficiency of timber processors in Ondo State, Nigeria, using Data Envelopment Analysis. Multi stage sampling technique was used to select two Local Government Areas with the highest number of sawmills, from each of which twenty saw millers were randomly selected, given a total of forty saw millers. Based on Constant Return to Scale Technical Efficiency, 35% of the saw millers were technically efficient while on the basis of Variable Return to Scale TE, 60% of the saw millers were technically efficient. About 35% of the saw millers were scale efficient. The Data Envelopment Analysis output revealed that 35% of the sampled saw millers were both technically and scale efficient and were hence operating at the most productive scale size. About 65% of the saw millers were operating at sub-optimal condition. Excesses in input utilization were observed in respect of total fixed cost, costs of electricity, servicing of mill, timber from forest reserve and operation of truck; and remuneration of labour. The inefficient firms should be encouraged to emulate the operating practices of the most productive firms so as to improve their performance.</p>

Hyper Threading Technology in Hardware Architecture for Processor Efficiency Enhancement

Intel’s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a micro architecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources. This paper describes the Hyper-Threading Technology architecture of Intel’s first implementation on the Intel Xeon processor family. Hyper-Threading Technology is an important addition to Intel’s enterprise product line and will be integrated into a wide variety of products.

Assessment of the Technical Efficiency of Gari Processing in Kwara State

This study was designed to carry out an analysis of the technical efficiency of gari processing in Kwara State, Nigeria. A three-stage random sampling technique was used to select a total of 120 gari processors used for the study. Stochastic Frontier Model (SFM) was used to analyse the data. Results of the SFM revealed that raw cassava and labour input were the main significant variables affecting gari processing in the study area. The level of technical efficiency of the processors was estimated at an average of 91%. Gamma (a) value of 0.559 however showed that 56% of the variation in the efficiency of the processors from the frontier was due to the inefficiency of the processors. The significant variables affecting the technical efficiency of gari processors were the education status and membership of cooperative association. The study therefore recommends the need for the processors to increase gari productivity and their through better and efficient resource utilization.

Simulation-based evaluation of the Imagine stream processor with scientific programs

This paper evaluates the performance and efficiency of Imagine stream processor for scientific programs. It classifies scientific programs into three classes based on their computation to memory access ratios. Typical programs are selected and measured on a simulated Imagine and two general-purpose processors. Comparative analysis is made with special attentions on the computational efficiency, power efficiency and performance bottleneck. The results show that programs in Class 1 attain high performance and high computational efficiency on Imagine. Their performance is only restricted by limited ILP and load imbalance across ALUs. Programs in Class 2 attain moderate performance but non-satisfactory computational efficiency on Imagine due to limited LRF and SRF reuse. Programs in Class 3 attain extremely low performance on Imagine because most of the execution time is spent on DRAM accesses. The estimated power efficiency on Imagine is excellent except for programs in Class 3.

Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime

Power consumption has become a major cause of concern spanning from data centres to handheld devices. Traditionally, improvement in power-performance efficiency of a modern superscalar processor came from technology scaling. However, that is no longer the case. Many of the current systems deploy coarse grain voltage and/or frequency scaling for power management. These techniques are attractive, but limited because of their granularity of control and effectiveness in nano-complementary metal-oxide-semiconductor (CMOS) technologies. This study proposes a novel architecture-level mechanism to exploit intra-thread variations for power-performance efficiency in modern superscalar processors. This class of processors implement several buffer/queue structures to support speculative out-of-order execution for performance enhancement. Applications may not need full capabilities of such structures at all times. A mechanism that collaboratively adapts a finite set of key hardware structures to the changing programme behaviour can allow the processor to operate with heterogeneous power-performance capabilities. This study presents a novel offline regression-based empirical model to estimate structure resizing for a selected set of structures. It is shown that using a few processor runtime events, the system can dynamically estimate structure resizing to exploit power-performance efficiency. Results show that using the proposed empirical model, a selective set of key structures can be resized at runtime to deliver on average 40% power-performance efficiency over a baseline design, with only 5% loss of performance.

An analysis of power reduction in datacenters using heterogeneous chip multiprocessors

Power and design constraints have forced the semiconductor industry to look at alternate solutions like heterogeneous chip multiprocessors to continue application performance scaling and improve energy efficiency of multicore processors. In this paper, we present an opportunity analysis of heterogeneous chip multiprocessors in the context of datacenter environments where applications often have latency SLAs. Specifically, we define three use cases of heterogeneous processors for datacenter applications and adopt an analytical approach to quantify relative energy savings of using heterogeneous processors over area-equivalent homogeneous configurations. Based upon our findings, we discuss the practical merits of heterogeneous chip multiprocessors in datacenters, including the issues that must be addressed in order to realize the theoretical benefits.

Understanding sources of ineffciency in general-purpose chips

Scaling the performance of a power limited processor requires decreasing the energy expended per instruction executed, since energy/op * op/second is power. To better understand what improvement in processor efficiency is possible, and what must be done to capture it, we quantify the sources of the performance and energy overheads of a 720p HD H.264 encoder running on a general-purpose four-processor CMP system. The initial overheads are large: the CMP was 500 x less energy efficient than an Application Specific Integrated Circuit (ASIC) doing the same job. We explore methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding. Broadly applicable optimizations like single instruction, multiple data (SIMD) units improve CMP performance by 14 x and energy by 10x, which is still 50x worse than an ASIC. The problem is that the basic operation costs in H.264 are so small that even with a SIMD unit doing over 10 ops per cycle, 90% of the energy is still overhead. Achieving ASIC-like performance and effciency requires algorithm-specifc optimizations. For each subalgorithm of H.264, we create a large, specialized functional/storage unit capable of executing hundreds of operations per instruction. This improves energy effciency by 160x (instead of 10x), and the final customized CMP reaches the same performance and within 3x of an ASIC solution's energy in comparable area.

Mobile processors for energy-efficient web search

As cloud and utility computing spreads, computer architects must ensure continued capability growth for the data centers that comprise the cloud. Given megawatt scale power budgets, increasing data center capability requires increasing computing hardware energy efficiency. To increase the data center's capability for work, the work done per Joule must increase. We pursue this efficiency even as the nature of data center applications evolves. Unlike traditional enterprise workloads, which are typically memory or I/O bound, big data computation and analytics exhibit greater compute intensity. This article examines the efficiency of mobile processors as a means for data center capability. In particular, we compare and contrast the performance and efficiency of the Microsoft Bing search engine executing on the mobile-class Atom processor and the server-class Xeon processor. Bing implements statistical machine learning to dynamically rank pages, producing sophisticated search results but also increasing computational intensity. While mobile processors are energy-efficient, they exact a price for that efficiency. The Atom is 5× more energy-efficient than the Xeon when comparing queries per Joule. However, search queries on Atom encounter higher latencies, different page results, and diminished robustness for complex queries. Despite these challenges, quality-of-service is maintained for most, common queries. Moreover, as different computational phases of the search engine encounter different bottlenecks, we describe implications for future architectural enhancements, application tuning, and system architectures. After optimizing the Atom server platform, a large share of power and cost go toward processor capability. With optimized Atoms, more servers can fit in a given data center power budget. For a data center with 15MW critical load, Atom-based servers increase capability by 3.2× for Bing.

기계식 쿨링 기법에 따른 고성능 멀티코어 프로세서의 냉각 효율성 분석

사용자들의 높은 요구 사항을 만족시키는 컴퓨팅 시스템을 개발하기 위해 프로세서의 성능을 향상시키기 위한 연구는 지속적으로 진행되어 왔다. 공정 기술 발달을 비롯한 다양한 기술 발전을 통하여 프로세서의 성능은 비약적으로 발전하였으나 그 이면에는 새로운 문제들이 발생하게 되었다. 그 중에서, 최근 들어 주된 문제점 중 하나로 인식되고 있는 열섬 현상은 칩의 신뢰성에 심각한 영향을 미치기 때문에 프로세서 설계 시 성능, 전력 효율성과 함께 반드시 고려되어야 한다. 과거에는 기계적인 냉각 기법으로 프로세서의 온도를 효과적으로 제어할 수 있었지만, 최근에는 프로세서의 성능이 높아져 발생되는 온도가 높아 냉각 비용이 급속히 증가하고 있다. 이로 인해, 최근의 온도 제어 연구는 기계적인 냉각 기법보다는 구조적 기법을 통한 온도 제어에 더욱 집중되는 추세를 보이고 있다. 하지만, 구조적 기법을 통해 온도를 제어하는 방안은 프로세서의 온도를 낮추는 데에는 효율적이지만 이를 위해 성능을 희생한다는 단점이 존재한다. 따라서, 기계적 냉각 기법을 통해 프로세서의 온도를 효율적으로 제어할 수 있다면, 성능 저하가 발생되는 구조적 기법을 통한 온도 제어기법의 사용 빈도가 줄어 그 만큼 성능이 향상될 수 있을 것으로 기대된다. 본 논문에서는 고성능 멀티코어 프로세서에서 발생하는 온도를 기계적인 냉각 기법이 얼마나 효율적으로 제어할 수 있는지를 상세하게 분석해 보고자 한다. 공랭식 냉각기와 수랭식 냉각기를 이용하여 다양한 실험을 수행한 결과, 공랭식 냉각기와 비교하여 수랭식 냉각기가 온도를 효과적으로 제어하는 반면에 전력 소모가 더 많음을 확인할 수 있다. 특히, 1W의 전력을 통해 낮출 수 있는 온도를 분석해 보면 공랭식에 비해서 수랭식이 더 효율적임을 알 수 있으며, 수랭식 냉각기의 경우에는 냉각 단계가 냉각 효율은 오히려 감소하게 됨을 확인할 수 있다. 실험 결과를 바탕으로 온도에 따라 적절하게 기계적 냉각 기법을 활용한다면 프로세서의 온도를 더욱 효과적으로 제어할 수 있을 것으로 기대된다. Many researchers have studied on the methods to improve the processor performance. However, high integrated semiconductor technology for improving the processor performance causes many problems such as battery life, high power density, hotspot, etc. Especially, as hotspot has critical impact on the reliability of chip, thermal problems should be considered together with performance and power consumption when designing high-performance processors. To alleviate the thermal problems of processors, there have been various researches. In the past, mechanical cooling methods have been used to control the temperature of processors. However, up-to-date microprocessors causes severe thermal problems, resulting in increased cooling cost. Therefore, recent studies have focused on architecture-level thermal-aware design techniques than mechanical cooling methods. Even though architecture-level thermal-aware design techniques are efficient for reducing the temperature of processors, they cause performance degradation inevitably. Therefore, if the mechanical cooling methods can manage the thermal problems of processors efficiently, the performance can be improved by reducing the performance degradation due to architecture-level thermal-aware design techniques such as dynamic thermal management. In this paper, we analyze the cooling efficiency of high-performance multicore processors according to mechanical cooling methods. According to our experiments using air cooler and liquid cooler, the liquid cooler consumes more power than the air cooler whereas it reduces the temperature more efficiently. Especially, the cost for reducing <TEX>$1^{\circ}C$</TEX> is varied by the environments. Therefore, if the mechanical cooling methods can be used appropriately, the temperature of high-performance processors can be managed more efficiently.

Development and design of experiments optimization of a high temperature proton exchange membrane fuel cell auxiliary power unit with onboard fuel processor

In this work, the concept development, system layout, component simulation and the overall DOE system optimization of a HT-PEM fuel cell APU with a net electric power output of 4.5 kW and an onboard methane fuel processor are presented. A highly integrated system layout has been developed that enables fast startup within 7.5 min, a closed system water balance and high fuel processor efficiencies of up to 85% due to the recuperation of the anode offgas burner heat. The integration of the system battery into the load management enhances the transient electric performance and the maximum electric power output of the APU system. Simulation models of the carbon monoxide influence on HT-PEM cell voltage, the concentration and temperature profiles within the autothermal reformer (ATR) and the CO conversion rates within the watergas shift stages (WGSs) have been developed. They enable the optimization of the CO concentration in the anode gas of the fuel cell in order to achieve maximum system efficiencies and an optimized dimensioning of the ATR and WGS reactors. Furthermore a DOE optimization of the global system parameters cathode stoichiometry, anode stoichiometry, air/fuel ratio and steam/carbon ratio of the fuel processing system has been performed in order to achieve maximum system efficiencies for all system operating points under given boundary conditions.