Processor Design Research Articles

Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with supply voltage as 0.8V at 1GHz. The proposed HFA consumes a power of 1.555uw, and the delay is 36.692ns. Layout designs are drawn for both 6T-XOR/XNOR-cell, and 1- bit HFA designs. XOR/XNOR-cells are designed based on the combination of normal CMOS-inverter and Pass Transistor Logic (PTL). Which is used in the design of high end device processors such as ALU that can be implemented for the IoT- design applications?

Design Methodologies for Integrated Quantum Frequency Processors

Frequency-encoded quantum information offers intriguing opportunities for quantum communications and networking, with the quantum frequency processor paradigm—based on electro-optic phase modulators and Fourier-transform pulse shapers—providing a path for scalable construction of quantum gates. Yet all experimental demonstrations to date have relied on discrete fiber-optic components that occupy significant physical space and impart appreciable loss. In this article, we introduce a model for the design of quantum frequency processors comprising microring resonator-based pulse shapers and integrated phase modulators. We estimate the performance of single and parallel frequency-bin Hadamard gates, finding high fidelity values that extend to frequency bins with relatively wide bandwidths. By incorporating multi-order filter designs as well, we explore the limits of tight frequency spacings, a regime extremely difficult to obtain in bulk optics. Overall, our model is general, simple to use, and extendable to other material platforms, providing a much-needed design tool for future frequency processors in integrated photonics.

Design and analysis of optical nano electro-mechanical-system-based logic circuits relied on movable waveguides

An approach based on optical nano electro-mechanical-system (NEMS) switches is proposed in this paper to develop low-power logic circuits and processors. Based on the specific logic tasks expressed by sum-of-products (SOP) expressions, an array of switches can be appropriately arranged to implement various logic circuits. The logical output can be detected by translating the presence or absence of the light in the optical guided mode, which is controlled by the displacement of NEMS actuators under electrostatic forces. Therefore, to show the universality of the proposed method and its capability to extend processor circuits, the operation of a MUX (2:1) is analyzed. Furthermore, the presented switch’s functional characteristics and the logic circuits’ optical performance are obtained using the Finite Element Method (FEM) and Finite Difference Time Domain (FDTD) approaches. According to simulation results, the properties of the proposed switch, such as the operating voltage and the switching time, are 12 V and 2.6 μs, respectively. Consequently, the proposed fast and low-power actuator can be a promising choice for realizing low-power digital circuits, especially in the design of NEMS processors for low-power applications because of the significant reduction in its power consumption and immunity against electromagnetic radiation.

Manipulating electromagnetic waves in a cavity-waveguide system with nontrivial and trivial modes.

The coupled cavity-waveguide approach provides a flexible platform to design integrated photonic devices that are widely applied in optical communications and information processing. Topological photonic crystals that can excite the nontrivial edge state (ES) and corner state (CS) have an unprecedented capability to manipulate electromagnetic (EM) waves, leading to a variety of unusual functionalities that are impossible to achieve with conventional cavity-waveguide systems. In this Letter, two-dimensional photonic crystals consisting of an ES waveguide, a CS cavity, and a trivial cavity are proposed as a means to robustly control the transmission characteristics of electromagnetic waves. As a proof-of-principle example, the analog of electromagnetically induced transparency (EIT) that is tolerated in disorders due to the robustness of the CS is numerically demonstrated. In addition, the analog of multi-EIT is also verified by introducing a trivial cavity with two degenerate orthogonal modes. This unique approach for robustly manipulating EM waves may open an avenue to the design of high-performance filters, modulators, and on-chip processors.

A computational design of a programmable biological processor

Basic synthetic information processing structures, such as logic gates, oscillators and flip-flops, have already been implemented in living organisms. Current implementations of these structures have yet to be extended to more complex processing structures that would constitute a biological computer. We make a step forward towards the construction of a biological computer. We describe a model-based computational design of a biological processor that uses transcription and translation resources of the host cell to perform its operations. The proposed processor is composed of an instruction memory containing a biological program, a program counter that is used to address this memory, and a biological oscillator that triggers the execution of the next instruction in the memory. We additionally describe the implementation of a biological compiler that compiles a sequence of human-readable instructions into ordinary differential equation-based models, which can be used to simulate and analyse the dynamics of the processor. The proposed implementation presents the first programmable biological processor that exploits cellular resources to execute the specified instructions. We demonstrate the application of the described processor on a set of simple yet scalable biological programs. Biological descriptions of these programs can be produced manually or automatically using the provided compiler.

Rapid and Accurate PPA Prediction for the Template-Based Processor Design Methods

The template-based chip design method aims to build rapidly. However, it still need synthesis and simulation flows to get the performance, power, and area (PPA) reports and find the proper parameters set in the design space exploration, which takes a long time. Therefore, a rapid and accurate PPA prediction method is proposed. At first, the PPA Prediction Model based on Multivariate Linear regression (ML-PM) is proposed to fit the multiple parameters’ influence on the PPA via the single parameter affection. Moreover, a Multivariate NonLinear regression Prediction Model (MNL-PM) based on Amdahl’s law is introduced to improve the accuracy of the PPA estimation. The empirical evaluation of the method shows that the PPA prediction for the template-based chip design methods can reach 98.60%, 99.19%, and 98.53% accuracy on performance, power, and, area separately, when compared with the PPA generated via the synthesis and simulation flows.

Design of Convolutional Neural Network Processor Based on FPGA Resource Multiplexing Architecture.

As CNNs are widely used in fields such as image classification and target detection, the total number of parameters and computation of the models is gradually increasing. In addition, the requirements on hardware resources and power consumption for deploying CNNs are becoming higher and higher, leading to CNN models being restricted to certain specific platforms for miniaturization and practicality. Therefore, this paper proposes a convolutional-neural-network-processor design with an FPGA-based resource-multiplexing architecture, aiming to reduce the consumption of hardware resources and power consumption of CNNs. First, this paper takes a handwritten-digit-recognition CNN as an example of a CNN design based on a resource-multiplexing architecture, and the prediction accuracy of the CNN can reach 97.3 percent by training and testing with Mnist dataset. Then, the CNN is deployed on FPGA using the hardware description language Verilog, and the design is optimized by resource multiplexing and parallel processing. Finally, the total power consumption of the system is 1.03 W and the power consumption of the CNN module is 0.03 W under the premise of guaranteeing the prediction accuracy, and the prediction of a picture is about 68,139 clock cycles, which is 340.7 us under a 200 MHz clock. The experimental results have obvious advantages in terms of resources and power consumption compared with those reported in related articles in recent years, and the design proposed in this paper.

A Neuromorphic Processing System With Spike-Driven SNN Processor for Wearable ECG Classification.

This paper presents a neuromorphic processing system with a spike-driven spiking neural network (SNN) processor design for always-on wearable electrocardiogram (ECG) classification. In the proposed system, the ECG signal is captured by level crossing (LC) sampling, achieving native temporal coding with single-bit data representation, which is directly fed into an SNN in an event-driven manner. A hardware-aware spatio-temporal backpropagation (STBP) is suggested as the training scheme to adapt to the LC-based data representation and to generate lightweight SNN models. Such a training scheme diminishes the firing rate of the network with little plenty of classification accuracy loss, thus reducing the switching activity of the circuits for low-power operation. A specialized SNN processor is designed with the spike-driven processing flow and hierarchical memory access scheme. Validated with field programmable gate arrays (FPGA) and evaluated in 40 nm CMOS technology for application-specific integrated circuit (ASIC) design, the SNN processor can achieve 98.22% classification accuracy on the MIT-BIH database for 5-category classification, with an energy efficiency of 0.75 μJ/classification.

A Facial Recognition System

Abstract: This paper introduces the design, implementation, and validation of a Digital Signal Processor (DSP) -based Prototype face recognition and authentication system. This system is designed to capture image sequences, detect facial features in photos, and detect and verify a person. The current application uses images captured on a webcam and compares them to archived websites using the Comprehensive Component Analysis (PCA) and Discrete Cosine Transform (DCT) methods. Initially, realtime verification of the captured images was performed using a PC-based program with algorithms developed in MATLAB. Next, the TMS320C6713DSP-based prototype system is upgraded and validated in real-time. Several tests are performed on different sets of images, and the performance and speed of the proposed system are measured in real-time. Finally, the result confirmed that the proposed system could be used in a variety of applications that are not possible in standard PC-based applications. Also, better results were seen from DCT analysis than PCA results.

Pulsed Laser Ranging Techniques Based on Digital Signal Processing Methods for Proximity Fuze

Laser fuze systems play an emerging part in military technology bases nowadays. In the paper, a solution is developed to improve the accuracy of the laser rangefinder system in laser fuze without changing the hardware design of the digital signal processor. The proposed algorithm will combine real-time pulse processing techniques used in target range measurement. The new algorithm interpolates returned data using a relatively low sampling rate to a higher one. It applies a cross-correlation technique using high-resolution reference waveform models to restore the position of the super-sampled start and return pulses. Based on the Monte Carlo method and simulating the waveform in the noise environments, 100 trials were judged on the standard deviation of the range estimations. With the presentation of detection performance comparison results between range estimation algorithms of laser fuzes, this paper can provide guidance and references for the application in the proximity fuze.

Retrieval and Characteristic Analysis of Multimedia Tester Based on Bragg Equation

Abstract In order to solve the problem of Bragg equation, a research on retrieval and feature of multimedia testing machine is proposed. Firstly, this paper investigates the various stages of multimedia retrieval system and some mainstream multimedia retrieval algorithms, in order to cover all aspects of relevant algorithms. Secondly, on the basis of investigation, eight representative algorithms are selected. These algorithms cover three stages of multimedia retrieval system, including feature extraction stage, feature matching stage and geometric verification stage. Based on the above observed characteristics, finally, some relevant suggestions on architecture design and system optimization are put forward, including the design of single node processor, the design in parallel environment and the suggestions for simulation and evaluation using this test set.

Electric-field control of nonlinear THz spintronic emitters

Energy-efficient spintronic technology holds tremendous potential for the design of next-generation processors to operate at terahertz frequencies. Femtosecond photoexcitation of spintronic materials generates sub-picosecond spin currents and emission of terahertz radiation with broad bandwidth. However, terahertz spintronic emitters lack an active material platform for electric-field control. Here, we demonstrate a nonlinear electric-field control of terahertz spin current-based emitters using a single crystal piezoelectric Pb(Mg1/3Nb2/3)O3–PbTiO3 (PMN–PT) that endows artificial magnetoelectric coupling onto a spintronic terahertz emitter and provides 270% modulation of the terahertz field at remnant magnetization. The nonlinear electric-field control of the spins occurs due to the strain-induced change in magnetic energy of the ferromagnet thin-film. Results also reveal a robust and repeatable switching of the phase of the terahertz spin current. Electric-field control of terahertz spintronic emitters with multiferroics and strain engineering offers opportunities for the on-chip realization of tunable energy-efficient spintronic-photonic integrated platforms.

Performance of superconducting quantum computing chips under different architecture designs

Existing and near-term quantum computers can only perform two-qubit gates between physically connected qubits. Research has been done on compilers to rewrite quantum programs to match hardware constraints. However, the quantum processor architecture, in particular the qubit connectivity and topology, still lacks enough discussion, while it potentially has a huge impact on the performance of the quantum algorithms. We perform a quantitative and comprehensive study on the quantum processor performance under different qubit connectivity and topology. We select ten representative design models with different connectivities and topologies from quantum architecture design space and benchmark their performance by running a set of standard quantum algorithms. It is shown that a high-performance architecture almost always comes with a design with a large connectivity, while the topology shows a weak influence on the performance in our experiment. Different quantum algorithms show different dependence on quantum chip connectivity and topologies. This work provides quantum computing researchers with a systematic approach to evaluating their processor design.

Design And Implementation of A MIPS Processor with Signal Processing Extensions On FPGA

Design And Implementation of A MIPS Processor with Signal Processing Extensions On FPGA

Prospects for using soft processors in systems-on-a-chip based on field-programmable gate arrays

Objectives. Developing the element base of field-programmable gate arrays (FPGA) may significantly affect the design of electronic devices due to the enhanced logical capacity of such chips and the general tendency towards increased subsystem integration. The system-on-a-chip (SoC) concept is aimed at combining receiving, processing, and exchange subsystems onto a single chip, as well as at implementing control, diagnostic, and other auxiliary subsystems. The study aimed at developing a method for soft processor applications, i.e., processors based on configurable logical resources, for implementing control functions in an FPGA-based SoC.Methods. A digital system design methodology was used.Results. For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered. In particular, such parameters as instruction set addressness, number of pipeline cycles, and arithmetic logic unit configuration are adjustable at the design stage to allow the optimization of the soft processor in the discrete parameter space. An approach to rapid prototyping of the assembler based on stack-oriented programming language with regular grammar was also considered. The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors. An implementation is considered on the example of an SoC based on Xilinx Virtex-7 FPGA containing several processor cores developed using the proposed methodology.Conclusions. The considered approaches to soft processor design allow the rapid prototyping of the control processor core for operation as part of an FPGA-based SoC.

Early Termination Based Training Acceleration for an Energy-Efficient SNN Processor Design.

In this paper, we present a novel early termination based training acceleration technique for temporal coding based spiking neural network (SNN) processor design. The proposed early termination scheme can efficiently identify the non-contributing training images during the training's feedforward process, and it skips the rest of the processes to save training energy and time. A metric to evaluate each input image's contribution to training has been developed, and it is compared with pre-determined threshold to decide whether to skip the rest of the training process. For the threshold selection, an adaptive threshold calculation method is presented to increase the computation skip ratio without sacrificing accuracy. Timestep splitting approach is also employed to allow more frequent early termination in split timesteps, thus leading to more computation savings. The proposed early termination and timestep splitting techniques achieve 51.21/42.31/93.53/30.36% reduction of synaptic operations and 86.06/64.63/90.82/49.14% reduction of feedforward timestep for the training process on MNIST/Fashion-MNIST/ETH-80/EMNIST-Letters dataset, respectively. The hardware implementation of the proposed SNN processor using 28 nm CMOS process shows that the SNN processor achieves the training energy saving of 61.76/31.88% and computation cycle reduction of 69.10/36.26% on MNIST/Fashion-MNIST dataset, respectively.

System design and research of multi-channel electroacupuncture instrument

This paper introduces the development history, working principle, curative effect under different output waveforms and the hardware and software design of the system. The proportional constant current output circuit is analyzed in detail. A system structure of electroacupuncture instrument based on modular design is proposed. The system structure mainly includes multi-channel electroacupuncture control module and display control module, which are connected through CAN bus. Multi-channel electroneedle control module adopts embedded processor and real-time operating system design, display control module is application level processor, running embedded Linux system design. The system has reasonable structure design and high expansibility, which is convenient for further research.

The Design and Simulation of a Novel Optical Adder Depending on Optical Tri-state Gates

Essential approaches involving photons are among the most common uses of parallel optical computation due to their recent invention, ease of production, and low cost. As a result, most researchers have concentrated their efforts on it. The Basic Arithmetic Unit BAU is built using a three-step approach that uses optical gates with three states to configure the circuitry for addition, subtraction, and multiplication. This is a new optical computing method based on the usage of a radix of (2): a binary number with a signed-digit (BSD) system that includes the numbers -1, 0, and 1. Light with horizontal polarization (LHP) (↔), light with no intensity (LNI) (⥀), and light with vertical polarization (LVP) (↨) is represented by -1, 0, and 1, respectively. This research proposes new processor designs for addition. As a result, the design can achieve m addition operations with an operand length of n bits simultaneously. To explain and justify the theoretical design idea, the three steps of adding a BSD are numerically simulated. The constructing process is thought to be more precise and faster because the time to add does not depend on the length of the word. For all entries, all bits are implemented simultaneously, boosting the system's efficiency. A simulation model for six addition processes with a total bit count of 15 bits across all entries is presented in this work performing in a one-time parallelism manner.

LSMCore: A 69k-Synapse/mm2 Single-Core Digital Neuromorphic Processor for Liquid State Machine

Neuromorphic processors have gained momentum recently due to their high energy efficiency in artificial intelligence applications compared to DNN accelerators. Most neuromorphic processors are executing SNNs (Spiking Neural Networks). Liquid State Machine (LSM), as the spiking version of reservoir computing, shows advantages and great potential in image classification, speech recognition, language translation, etc.. Comparing with other SNN models, LSM has the characteristics of easy to train and low resource utilization, which is suitable for low-power and resource-constrained edge computing scenarios. In this paper, we propose a novel design of a neuromorphic processor, LSMCore, aiming at LSM acceleration. LSMCore supports both training and inference of LSM. It consists of 256 input neurons, 1024 liquid neurons, and 1.31M synapses. Besides, multiple optimization techniques, including weight quantization for reducing storage, zero-skipping for decreasing dynamic sparsity, and mini-batch training are adopted in this processor. The experimental results show that the frequency of LSMCore achieves 400 MHz, the power is 4.9W and the area is 18.49 mm² with a 40nm library. Comparing with the baseline, LSMCore achieves up to <inline-formula> <tex-math notation="LaTeX">$80.7\times $ </tex-math></inline-formula>(<inline-formula> <tex-math notation="LaTeX">$49.6\times $ </tex-math></inline-formula>), <inline-formula> <tex-math notation="LaTeX">$91.3\times $ </tex-math></inline-formula>(<inline-formula> <tex-math notation="LaTeX">$56.3\times $ </tex-math></inline-formula>), and <inline-formula> <tex-math notation="LaTeX">$83.1\times $ </tex-math></inline-formula>(<inline-formula> <tex-math notation="LaTeX">$56.8\times $ </tex-math></inline-formula>) speedup on MNIST, N-MNIST, and Free Spoken Digital Dataset (FSDD) respectively for training (inference), while the accuracy of LSMCore on these three datasets are 96.8&#x0025;, 97.6&#x0025;, and 90&#x0025; respectively.

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT

Offloading the unprecedented growing data to the edge exhibits a mainstream trend in the Industrial Internet of Things (IIoT) era, delivering far-reaching impacts in all aspects of our daily lives, including transportation, health care, and entertainment. However, voluminous data analyzes and processing at the edge will unavoidably raise the edge processor's burden and dramatically expand its design complexity and energy dissipation. This article proposes a flexible bit-adjustment-based energy-efficient convolution module with an approximate divide-and-conquer (ADC) multiplier for compact and low-power edge processor design. The maximum distribution search technique is utilized to exploit the optimal fixed-point representation format for both input and output of the convolution module. The neural network manifests the same precision as a 32-b floating-point multiplication deploying the determined representation formats. An ADC multiplier is proposed to realize the convolution module by eliminating the high-bit multiplication between weights and feature maps. The dynamic power consumption of the ADC multiplier-based convolution module with the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(6, 9)$</tex-math></inline-formula> input and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(7, 8)$</tex-math></inline-formula> output representation formats is 3.85% lower than that of the 16-b signed multiplication circuit. Furthermore, the dynamic power consumption with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(6, 9)$</tex-math></inline-formula> input is capable of being decreased by 15.38% for the 16-b convolution if the output is represented by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(1, 14)$</tex-math></inline-formula> format and by up to 39.93% for the 64-b multiplication. The practical verification system of the convolution module working on a field-programmable gate array evaluation board exhibits an outstanding low-power characteristic.