Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

Abstract

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with supply voltage as 0.8V at 1GHz. The proposed HFA consumes a power of 1.555uw, and the delay is 36.692ns. Layout designs are drawn for both 6T-XOR/XNOR-cell, and 1- bit HFA designs. XOR/XNOR-cells are designed based on the combination of normal CMOS-inverter and Pass Transistor Logic (PTL). Which is used in the design of high end device processors such as ALU that can be implemented for the IoT- design applications?