Processor Chip Research Articles

GUI Based 6-DOF Robotic Arm for Radioactive Element Handling

Abstract: Dealing with radioactive elements while research can be dangerous as it can have acute or passive effects on humans. In present scenario research is conducted on radioactive elements by humans after Wearing personal protective equipment such as coat, gloves, safety glasses and close-toed shoes. This equipment provide protection to some extend but still prolonged exposure to radio-active element or some accident can lead to great loss in human life. We can use 3 joint moving robotic arm controlled by GUI to handle radioactive elements while research. This will stop the human exposure to the harmful waves and also reduce chances of accident. The robotic arm has three joints controlled by Four servo-motors. These three joints allows the robotic arm to move to any point in the 3d plane and pick and place objects. The movement of the robotic arm and each of its joints can be controlled from any device with Wi-Fi & Bluetooth capability. An intuitive GUI is displayed in the browser of controlling device. The remote controlled properties and the control of movement is powered by ESP32 module. ESP32 is a system on chip processor which can be programmed as per requirement and has various I/O ports which allows for different motors and sensor connectivity. The ESP32 module is programmed from computer using Arduino IDE. C program is written & then uploaded on ESP-32. We’ve also added the functionality of recording action and then playing it once or multiple times by programming function of recording and playing action. The proposed system will reduce the requirement of humans while dealing with radioactive elements. The proposed system can perform various action on radioactive elements controlled from safe distance.

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

Reconfigurable multi-channel microwave photonic receiver for a multi-band signal based on cascaded microring resonator banks

What we believe to be a novel reconfigurable multi-channel microwave photonic (MWP) receiver for multi-band RF signal is demonstrated for the first time, to the best of our knowledge. A reconfigurable MWP signal processing chip based on two cascaded microring filter banks is employed in the proposed receiver, which slices the multi-band RF input into several narrow band signals and selects optical frequency comb lines for frequency converting of each channel. Due to the significant reconfigurability of the signal processing chip, the proposed receiver can flexibly choose the output frequency band of each channel, and thus different frequency components of the multi-band RF input can be down converted to the intermediate frequency (IF) band for receiving or converted to other frequency band for forwarding. A multi-band RF signal composed of a linear frequency modulation (LFM) signal with 2 GHz bandwidth and a quad-phase shift keyed (QPSK) signal with 100 Mbit/s rate is experimentally received and reconstructed by the proposed receiver, where the reconstructed LFM component exhibits a signal to noise ratio (SNR) of 10.2 dB, and the reconstructed QPSK component reaches a high SNR of 26.1 dB and a great error vector magnitude (EVM) of 11.73%. On the other hand, the QPSK component of the multi-band RF signal centered at 13.5 GHz is successfully converted to 3.1 GHz.

Research of chipper knives with a modified cutting edge for the production of dimensionally uniform wood chips

The paper is focused on the research of chipper knives with a straight and modified cutting edge in order to determine the energy consumption of the chipping process and the uniformity of the size of the fractions of the designed chipper knife for the production of dimensionally uniform chips. The research took place on two different tree species where the representative of the coniferous tree was the common spruce (Picea abies) and the deciduous tree was the winter oak (Quercus petraea). The research took place on a PTO-powered (power take off) disc chipping machine where it was not modified for research purposes. The results showed that a knife with a modified cutting edge is higher in terms of energy consumption than chipper knives with a straight cutting edge. From the evaluation of the sieve analysis for a chipper knife with a modified cutting edge, the energy chip of uniform granulometric composition is a homogeneous bulk material.

A Systematic Study on the Application of Computer Big Data Analysis to Improve the Accuracy of Referee Decision in Sports Events

Due to the complex working environment, long communication distance and high reliability requirements of referees in weightlifting events, this project uses TI's MSP430F5299 as its core processing chip. RS485 for long-distance communication. This system realizes a variety of judgments, arbitration supervision, system function setting, LED large screen display, PC data real-time transmission and other functions. Then, Fourier pyramid filtering method is used to extract human skeleton information, and SVM is used to classify human behavior to complete the construction of human behavior recognition model. The findings from the study indicate that the architectural approach detailed within this manuscript yields a higher degree of precision in identification, thereby offering judges an enhanced instrument for assessment.

Genotype-by-environment interactions and local adaptation shape selection in the US National Chip Processing Trial

Key messageWe find evidence of selection for local adaptation and extensive genotype-by-environment interaction in the potato National Chip Processing Trial (NCPT).We present a novel method for dissecting the interplay between selection, local adaptation and environmental response in plant breeding schemes. Balancing local adaptation and the desire for widely adapted cultivars is challenging for plant breeders and makes genotype-by-environment interactions (GxE) an important target of selection. Selecting for GxE requires plant breeders to evaluate plants across multiple environments. One way breeders have accomplished this is to test advanced materials across many locations. Public potato breeders test advanced breeding material in the National Chip Processing Trial (NCPT), a public–private partnership where breeders from ten institutions submit advanced chip lines to be evaluated in up to ten locations across the country. These clones are genotyped and phenotyped for important agronomic traits. We used these data to interrogate the NCPT for GxE. Further, because breeders submitting clones to the NCPT select in a relatively small geographic range for the first 3 years of selection, we examined these data for evidence of incidental selection for local adaptation, and the alleles underlying it, using an environmental genome-wide association study (envGWAS). We found genomic regions associated with continuous environmental variables and discrete breeding programs, as well as regions of the genome potentially underlying GxE for yield.

Advanced Packaging Trends in the Semiconductor Industry

Advanced packaging is an important technology that is now taking over from advanced processes to help the semiconductor industry continue to grow. The researcher found that the personnel in contact with the semiconductor industry chain have already had a preliminary understanding of advanced packaging, however, the future development trend of the advanced packaging industry still lacks a comprehensive knowledge. Therefore, the research topic of this paper is the development trend of advanced packaging industry. The research methodology of this paper is as follows: firstly, to understand the concept and development trend of advanced packaging, secondly, to list the factors driving the development of advanced packaging, and finally, to understand the development direction of international enterprises in advanced packaging. This paper finds that after the chip process technology has entered the "post-Moore era", advanced packaging has been widely used in the fields of high-end logic chips, memories, RF chips, image processing chips, touch chips and so on. Advanced packaging technology tends to be diversified in function, stacking and connection. According to Yole, a market research organization, the global share of advanced packaging in the IC packaging and testing market will continue to increase. At the same time, Yole predicts that the global compound annual growth rate of traditional packaging will be only 1.9% from 2019 to 2025, which is much lower than the growth rate of advanced packaging. Advanced packaging is the key path to improve system performance in the post-Moore era.

DISTRIBUSI DAN MARGIN PEMASARAN PRODUK OLAHAN OPAK SINGKONG DI KOTA KENDARI

Marketing is a crucial aspect of the agribusiness system. One potential agroindustry in Kendari City is cassava chips processing. Sampling was conducted using the snowball sampling method, identifying, selecting, and sampling respondents totaling 30 individuals, with the majority being cassava chip entrepreneurs who are housewives. These retail traders prefer direct marketing channels to reach more consumers and facilitate easier purchase of cassava chip products without having to buy directly from the production site. For marketing efficiency, results found for marketing channel I were 0.15%, while for channel II it was 7.26%. This approach also benefits retailers who obtain cassava chip products without going through wholesalers. In practice, there will be cost and revenue calculations incurred by both producers and marketing institutions involved, resulting in different outcomes and creating marketing margins. The larger the marketing margin, the less efficient the marketing activities become. This research aims to determine the distribution of marketing, the size of marketing margins, and the proportion of the price received by cassava chip producers (producer's share) from the retail price. The findings of this research are expected to provide benefits and increase income for the marketing institutions involved in promoting cassava chip products in Kendari City.

Research on sensing characteristics of microfluidic sensor based on photonic crystal fiber

To address the challenges associated with sample injection into the air hole of photonic crystal fiber (PCF) and collimation, in this paper, we assemble a single-mode photonic crystal single-mode fiber structure sensor chip based on the Mach–Zehnder interference principle using microfluidic chip processing technology. The sensing principle is analyzed mathematically and the sensing characteristics are verified theoretically and experimentally. The temperature sensitivity of the sensor is −1.3325 nm °C−1, and the refractive index sensitivity is 1666.2 nm RIU−1. This structure solves the difficulty of filling and coupling PCFs. Furthermore, it introduces a novel research methodology for the design and assembly of high-performance biosensors based on PCFs.

Measurement and Simulation of Mechanical Strength of Back-End-Of-Line Layer in Advanced CMOS Dies

The back-end-of-line (BEOL) layers of ICs are subjected to considerably high mechanical forces during processing and when operating in harsh conditions. Without proper design and flip chip process control, the forces induced from flip chip bumps may exceed the ultimate strength of the BEOL resulting in critical failures. It is therefore of high interest to have a measurement method to quantify the strength of the BEOL structure of a functional IC. Ultimate fracture stress values are extracted from these measurements which can be used in thermo-mechanical simulations of flip chip assemblies for survivability evaluations.

Study on the Manufacturability of XDFOI Package with Organic RDLs (XDFOI-O)

The concept of chiplet has been proposed in the post Moore era, while how to achieve the layout of multiple chips of different processes and sizes in the manufacturing process is a coming problem that needs to be considered. Different layouts may significantly affect the manufacturability during the packaging process. Prospective finite element analysis (FEA) can evaluate various layouts by optimizing the layout and increasing the placement of dummy chips as stiffeners, thereby selecting the best layout and combination method. In addition, the characteristic of chiplet packaging is that multiple chips may come from different sources, such as different foundries, processes, sizes, or even thicknesses. This really poses challenges to the subsequent flip chip and wafer thinning process for leveling the total package. It is necessary to confirm the evaluation of the impact of chips with different thicknesses and underfill coverage in the process, so as to ensure the consistency in processing and improve the yield of packages.

Design of enlarged-asymmetric-power single-mode silicon evanescent lasers with asymmetric distributed feedback gratings

Great achievements in the bonded III–V lasers have pushed the productization process of silicon photonic chips. In this work, we report the design of silicon evanescent lasers with asymmetric gratings, which can provide high output power and stable single-longitudinal-mode operation. The high coupling efficiency and low threshold current density are achieved by linearly expanding the width of rib waveguide from 0.4 µm to 2 µm through 150 µm taper coupler. By optimizing the λ/4 phase-shift position ratio from conventional 0.50 to 0.64, the ratio of output power at both sides of the bonded lasers (P2/P1) is improved from1.0 to 5.0, and the normalized grating coupling coefficient (κL) remains at 2.78. By optimizing the duty cycle at one side of λ/4 phase-shift from 0.5 to 0.8 and another side remains at 0.5, P2/P1 is 3.3, and κL lowers from 2.78 to 2.21. Besides, keeping the phase-shift position ratio at 0.64 while changing the duty cycle to 0.7, P2/P1 increases significantly to 7.5 with κL of 2.59. This work provides a step forward towards the development of high-power silicon-based light sources.

Design and fabrication of improved motorized plantain slicing machine for chips production

The majority of small-scale food companies and shops in Nigeria are unable to meet the enormous demand for plantain chips because of a few crucial considerations. Being a semi-perishable crop, a significant number of plantains are lost to deterioration at the highest point of harvest. Adopting an efficient method for turning food into chips for year-round availability and preservation is vital to guarantee food security and minimize waste. Plantain slicing with a knife has always been a hard, time-consuming, and unclean process with poor results. Although the slicer can be used for domestic purposes, it was intended for usage in medium and small-scale industries. The plantain slicing machine's design and construction aim to address the aforementioned issues. The design parameters that have been determined are the belt and pulley size, the power requirement (P), and the shaft diameter (D). The complete apparatus consists of a slider-crank mechanism that is powered by an electric motor through a v-belt. The driven pulley is supported by two bearings on a shaft. The hopper, which holds the plantains, the guide, and the stanchion make up the slider. Two cranks, one on each side, make up the mechanism. Through the use of a connecting rod, which transfers motion to the hopper (slider), they are connected to the slider. The intended chip formation is accomplished by moving the slider back and forth along the guide's bed, which holds the cutting blade. The device, which operates on the shear cutting concept, can cut raw plantains into chips with consistent sizes in a shorter amount of time. In just two to three seconds, it can cut a raw plantain finger up to 70 mm in diameter. According to the performance evaluation results, it takes an average of 267 seconds to slice 30 plantain pieces with an average length of 260 mm, weight of 0.3 kg, and diameter of 65 mm. All that's needed for machine maintenance is appropriate cleaning after usage and lubrication of the spinning parts. Even while this plantain slicer uses less labor and is more efficient than a chip cutter, it nevertheless yields chips with a consistent thickness. This updated device is easy to use, clean, lightweight, removable, and requires less maintenance. Consequently, the aforementioned constraints will be removed with this new design's enhancement, making the processing of plantain chips quite simple.

Efficient machine learning-assisted failure analysis method for circuit-level defect prediction

Integral to the success of transistor advancements is the accurate use of failure analysis (FA) which benefits in fine-tuning and optimization of the fabrication processes. However, the chip makers face several FA challenges as device sizes, structure, and material complexities scale dramatically. To sustain manufacturability, one can accelerate defect identification at all steps of the chip processing and design. On the other hand, as technologies scale below the nanometer nodes, devices are more sensitive to unavoidable process-induced variability. Therefore, metallic defects and process-induced variability need to be treated concurrently in the context of chip scaling, while failure diagnostic methods to decouple the effects should be developed. Indeed, the locating a defective component from thousands of circuits in a microchip in the presence of variability is a tedious task. This work shows how the SPICE circuit simulations coupled with machine learning based-physical modeling should be effectively used to tackle such a problem for a 6T-SRAM bit cell. An automatic bridge defect recognition system for such a circuit is devised by training a predictive model on simulation data. For feature descriptors of the model, the symmetry of the circuit and a fundamental material property are leveraged: metals (semiconductors) have a positive (negative) temperature coefficient of resistance up to a certain voltage range. Then, this work successfully demonstrates that how a defective circuit is identified along with its defective component's position with approximately 99.5 % accuracy. This proposed solution should greatly help to accelerate the production process of the integrated circuits.

Application of machine learning to SRAM circuit design

This paper discusses the application of machine learning in Static Random Access Memory (SRAM) circuit design. It mentions several aspects of application analysis, including SRAM design for machine learning applications, SRAM PUF design for machine learning modelling attacks, lightweight fault-tolerant mechanism for NVDLA-based edge AI chips, interconnection resource allocation of SRAM FPGAs using reinforcement learning and Markov decision process, and SRAM power optimization and privacy security using machine learning. This article conclude that machine learning can be used to model and optimize SRAM performance, improve system reliability and stability through fault detection and fault tolerance mechanisms, provide a more comprehensive and efficient approach to testing and verification, and automatically correct and repair errors. The significance of machine learning in SRAM design is to provide an intelligent method and tool that can speed up the design process, improve system performance, increase reliability, and drive the advancement of chip manufacturing and processes.

Towards large-scale programmable silicon photonic chip for signal processing

Abstract Optical signal processing has been playing a crucial part as powerful engine for various information systems in the practical applications. In particular, achieving large-scale programmable chips for signal processing are highly desirable for high flexibility, low cost and powerful processing. Silicon photonics, which has been developed successfully in the past decade, provides a promising option due to its unique advantages. Here, recent progress of large-scale programmable silicon photonic chip for signal processing in microwave photonics, optical communications, optical computing, quantum photonics as well as dispersion controlling are reviewed. Particularly, we give a discussion about the realization of high-performance building-blocks, including ultra-low-loss silicon photonic waveguides, 2 × 2 Mach–Zehnder switches and microring resonator switches. The methods for configuring large-scale programmable silicon photonic chips are also discussed. The representative examples are summarized for the applications of beam steering, optical switching, optical computing, quantum photonic processing as well as optical dispersion controlling. Finally, we give an outlook for the challenges of further developing large-scale programmable silicon photonic chips.

The Era of GAAFET Is About to Come

In recent years, with the development of the semiconductor industry, Moore’s Law has gradually become ineff ective, making it increasingly diffi cult for people to improve chip manufacturing processes. Many people believe that Moore’s Law will no longer exist. However, with Samsung announcing the production of 3-nanometer gate-all-around (GAA) architecture process technology chips on June 30, 2022, the chip process has been further advanced. Moore’s Law is expected to continue in the coming years. This article will mainly introduce why GAAFET will become the mainstream fi eld-eff ect transistor in the future. The potential problems that GAAFET may encounter in its future development will also be analyzed, including massive research and development costs and a longer research and development cycle.

Strengthening mechanisms and wear performance of Al/APC/micro-B4Cp hybrid composites prepared by HTCDC process and hot extrusion

An Al/APC/micro-B4Cp hybrid composites were fabricated using the hydrothermal carbonized deposition on chips (HTCDC) process and hot extrusion process. The microstructure and mechanical properties and wear resistance of the Al/APC/micro-B4Cp hybrid composites were characterized. APC spheres and irregular micro-B4Cp could be observed on the Al chips surface after the HTCDC process, and the micro-B4Cp were also coated with an APC film. Al/APC/micro-B4Cp hybrid composites were prepared by hot extrusion from the Al chips covered with APC and micro-B4Cp. With the increase of micro-B4Cp content, the α-Al grain sizes of composites decrease from 18.8 µm to 12.8 µm, because the dispersed micro-B4Cp in the composites can pin the grain boundaries, hinder the migration of grain boundaries, and inhibit the growth of recrystallized grains. The highest values were obtained when the micro-B4Cp content was 3 wt%, and the UTS and hardness values of Al/APC/B4Cp hybrid composites (223.66 MPa and 101.8HV) were increased by 14.07% and 24%, respectively, compared with Al/APC composite. The results of the YS calculation show that thermal mismatch strengthening is the main strengthening mechanism, followed by grain-refined strengthening, and load transfer strengthening. Because the APC of the self-lubricating effect can form a lubrication film on the wear surface during sliding, the COF and wear rate of the Al/APC composite are low. When the micro-B4Cp is added to the matrix, the micro-B4Cp will strip the APC film from the wear surface, so the COF increases. However, the addition of micro-B4Cp can greatly increase the hardness of the composite, as a consequence that the wear rate of the composite material is still low(1.44 ×10−5 mm3/Nm).

Non-contact surface thermal deformation measurement based on chromatic confocal sensor

Chromatic confocal sensors are widely used in chip processing, high-precision instrument manufacturing, industrial testing and other fields because of high-precision displacement recognitioncapabilities. This research combines a chromatic confocal device with resistance temperature detector for dynamic deformation measurement of heating pipeline. The system is suitable for the measuring range of 300 µm and resolution can reach 0.3 µm. Using finite element method to simulate thermal deformation of aluminium with a thickness of 2 mm, and obtaining simulation trends and results. The end face of aluminium is heated continuously and uniformly in experiment, recording the data of spectral, laser triangular displacement sensor, and temperature sensor at 10°C intervals, respectively. And using Gaussian fitting algorithm to obtain spectral peaks, the corresponding thermal deformation is obtained through the relationship between wavelength and axial displacement. The results show that the experimental data of the chromatic confocal sensor is consistent with the laser triangular displacement sensor basically, with a maximum standard deviation of 1.06. In addition, simulation and experimental trends are consistent.

Simultaneous high-speed cutting and high-feed milling: An investigation on surface integrity

In this article, the potential of high-speed machining with an inverse cutting ratio b/h < 1 (uncut width of chip b to uncut chip thickness h) is presented based on the evaluation of surface integrity. If the machining is realized with a low cutting ratio many process quantities and chip formation mechanisms are fundamentally changed. As a result, the cutting process is stabilized through reduced feed forces and improved chip removal conditions. For the investigations, face-milling trials were carried out on an aluminum alloy (EN AC-42100) under conventional and high cutting speeds with variation of the feed per tooth and the use of cemented carbide and polycrystalline diamond tools. It is shown that when both machining strategies are combined, there is no further reduction in force components or improvement in surface topography. When the feed per tooth is increased at high cutting speeds, there is a linear increase in force components but surface roughness remain almost unchanged. After an initial increase in surface residual stresses, increasing the cutting speed leads mainly to compressive surface residual stresses. Overall, the surface integrity is influenced by the choice of cutting material and the micro-geometry of the cutting edge radius.