Process Voltage Temperature Variations Research Articles

Continuous‐time four‐quadrant modulator with inherent PVT cancellation

A continuous-time four-quadrant multiplier in subthreshold region is presented. Besides its simplicity, the structure features inherent process–voltage–temperature (PVT) variation cancellation while working under low voltage supply and dissipating an ultra-low power. The PVT variation was alleviated through an inherent log/anti-log cancellation technique, making it as a good candidate for bio-potential acquisition systems. The input and output signals are currents resulting in a wider bandwidth and larger dynamic range compared with the voltage-mode counterparts. The circuit is versatile and can be configured as a modulator, frequency doubler, and linear variable gain amplifier as shown in theory and simulation results.

Analysis of the Impact of Variations on Signal Electro-Migration and Optimization of Interconnects in FinFET Designs.

The An AC current induced electro-migration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower and suffer from fast switching and large driving current from FinFETs. Thus, the high current density on those signal interconnects can cause a serious failure. In this paper, we analyze EM on signal interconnects in 16 nm FinFET design, and characterize the impact of process variations, e.g., lithography and etch process, CMP (chemical-mechanical polishing) process, redundant via, etc. We also analyze signal-line EM with transistor-level PVT (process-voltage-temperature) variation corners. Then we optimize the signal lines with various design approaches to mitigate EM problem in 16 nm design.

A Low‐Power Low‐Cost 780MHz CMOS FSK Receiver for Short‐Range Wireless Communication

This paper presents a low-power low-cost 780MHz CMOS Frequency shift keying (FSK) receiver for short-range wireless communication. A current-reused Low power amplifier (LNA) and a single-balance passive mixer are employed to cut down the current consumption of the RF frontend in receiver. A 3rd -order active-RC complex filter with reconfigurable bandwidth is implemented and a novel automatic tuning circuit is used in the filter to eliminate the negative effect of the Process, voltage, temperature (PVT) variations. A novel replica-circuit master-slave automatic tuning circuit and a discrete-time differentiator are employed in demodulator to keep the demodulation performances from the PVT variations and the frequency offset of Intermediate frequency (IF). The receiver is fabricated in 0.18µm CMOS and occupies a chip area of about 0.97mm2. It can achieve a sensitivity of –83.7dBm and a tolerance of IF range from 1.5MHz to 3.7MHz with a 4.7mA current consumption under a 1.8V supply.

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

As the semiconductor technology node scales into the deep submicrometer regime, it has become very difficult to obtain high IC yields because the process–voltage–temperature variations induce large spreads in delay and power. In this paper, we propose a new framework, called GenFin, which is, as far as we know, the first to target the multiobjective yield optimization of logic circuits. Since FinFETs are a promising substitute for CMOS at 22-nm technology node and beyond, we evaluate the framework with a 22-nm FinFET logic library. By combining the power of genetic algorithm (GA) and adaptive multiobjective optimization, GenFin produces a set of nondominated logic circuits whose timing, leakage power, and dynamic power yields are simultaneously optimized. This can help designers make tradeoff decisions wisely and avoid suboptimal solutions. We also propose an incremental statistical circuit analyzer, called incremental FinPrin, that speeds up the statistical static timing analysis by up to $9.6\times $ and the statistical power analysis by up to $2235.7\times $ , while incurring errors of only up to 0.031% in mean and 0.74% in standard deviation relative to nonincremental analysis. We use heuristics based on the deterministic timing analysis and gate criticality to reduce the GA search space and also improve the quality of its solutions. We present extensive experimental results to demonstrate the efficacy of GenFin.

PVT-independent dB-linear reconfigured local-feedback digital variable gain amplifier

This paper proposes a PVT (process, voltage, temperature)-independent dB-linear digital VGA (variable gain amplifier) using reconfigured local-feedback transconductance stages. By using the local-feedback stage, the transconductance is independent to the input voltage. With the reconfigured topology, the linearity in decibel of the voltage gain is improved. Moreover, the voltage gain is independent to PVT variations. Based on the post-layout simulation, the worst absolute value of the gain error is 0.33 LSB at the corner of [FF, 75°C]. The gain error is measured to be 0.32 LSB with dynamic gain range of 40.76dB (−23.58 to 17.18dB). When the frequency of the input signal is 20MHz and the control word is 0000, the P1dB and the NF are 21.14dBm and 0.048dB, respectively. The proposed design is implemented by using a typical 0.18μm CMOS process. The core area of the proposed design is 0.838×0.838mm2. The power consumption is measured to be 10.25mW for a 20pF capacitive load at 20MHz.

Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template

We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high operational robustness, high speed, and low power dissipation. There are five key features of our proposed SAHB. First, the SAHB cell embodies the async QDI 4-phase ( $4\phi )$ signaling protocol to accommodate process-voltage–temperature variations. Second, the sense amplifier (SA) block in SAHB cells embodies a cross-coupled latch with a positive feedback mechanism to speed up the output evaluation. Third, the evaluation block in the SAHB comprises both nMOS pull-up and pull-down networks with minimum transistor sizing to reduce the parasitic capacitance. Fourth, both the evaluation block and SA block are tightly coupled to reduce redundant internal switching nodes. Fifth, the SAHB cell is designed in CMOS static logic and hence appropriate for full-range dynamic voltage scaling operation for $\text{V}_{\mathrm {\mathbf {DD}}}$ ranging from nominal voltage (1 V) to subthreshold voltage ( $\sim 0.3$ V). When six library cells embodying our proposed SAHB are compared with those embodying the conventional async QDI precharged half-buffer (PCHB) approach, the proposed SAHB cells collectively feature simultaneous $\sim 64$ % lower power, $\sim 21$ % faster, and $\sim 6$ % smaller IC area; the PCHB cell is inappropriate for subthreshold operation. A prototype 64-bit Kogge-Stone pipeline adder based on the SAHB approach (at 65 nm CMOS) is designed. For a 1-GHz throughput and at nominal $\text{V}_{\mathrm {\mathbf {DD}}}$ , the design based on the SAHB approach simultaneously features $\sim 56$ % lower energy and $\sim 24$ % lower transistor count advantages than its PCHB counterpart. When benchmarked against the ubiquitous synchronous logic counterpart, our SAHB dissipates $\sim 39$ % lower energy at the 1-GHz throughput.

PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

This paper presents a new design of dopingless dynamically configurable double-gate tunnel FET (TFET) for process–voltage–temperature (PVT)-aware applications. The dopingless FETs have recently been explored and showed very good electrostatic control over the channel with reduced thermal budget and process complexity. The proposed device makes use of the dopingless concept, but instead of charge plasma, electrostatic doping is used for carrier concentration under the source/drain region that allows dynamic configuration. The 2-D device simulation results show that the proposed device has promising switching behavior and offers significant reduction in PVT variations on different performance metrics, such as subthreshold swing and drive current as compared with a conventional TFET.

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

A framework is proposed to analyze system-level reliability and evaluate the lifetimes of state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) variations and device wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD). This work studies not only the system performance degradation due to each wearout mechanism individually, but also the performance degradation while all these wearout mechanisms happen simultaneously. A unified gate-delay model is developed to combine PVT variations and the aging effect, and then a statistical timing engine is constructed to analyze performance degradations and system lifetimes.

Design, Test, and Repair of MLUT (Memristor Look-Up Table) Based Asynchronous Nanowire Reconfigurable Crossbar Architecture

The recently proposed nanoscale asynchronous crossbar architecture based on memristor-based look up table (MLUT) combines the advantages of nanoscale memristor crossbar technology and clockless logic paradigm for viable nanoscale computing. Potential technical merits of the proposed MLUT architecture includes: 1) better manufacturability due to structural simplicity and regularity; 2) improved robustness over PVT (process-voltage-temperature) variations; 3) event-driven low-power/noise asynchronous operation; and 4) encoding-level logic inversion. In spite of having numerous merits over the clocked counterparts and previous asynchronous designs, it is bound to have inevitable defects and faults due to nondeterministic and unconventional nanoscale assembly and operation. In order to overcome defect issues in the proposed MLUT-based nanoscale asynchronous crossbar architecture, there is a need to develop efficient design, test, and repair techniques. Typical approach so far has been to test every crosspoint on each crossbar MLUT exhaustively; this is not only laborious but is also prohibitively time and space consuming for designs involving large number of MLUTs. This paper introduces a novel testing scheme based on “Divide and Conquer” approach to efficiently locate the defective memristors in a MLUT. The proposed testing scheme leverages upon a special current additive property of the memristor-based multiplexer. It performs binary isolation of regions, reducing the search space by half whenever applicable. Numerical simulations clearly demonstrate that the approach is generic, deterministic, and scalable. A faster MLUT programming technique and a repair technique utilizing partially defective MLUTs are also proposed and extensively validated through parametric simulations.

Integrated Resource Allocation and Binding in Clock Mesh Synthesis

The clock distribution network in a synchronous digital circuit delivers a clock signal to every storage element, that is, clock sink in the circuit. However, since the continued technology scaling increases PVT (process-voltage-temperature) variation, the increase of clock-skew variation is highly likely to cause performance degradation or system failure at runtime. Recently, to mitigate the clock-skew variation, many researchers have taken a profound interest in the clock mesh network. However, though the structure of the clock mesh network is excellent in tolerating timing variations, it demands significantly high power consumption due to the use of excessive mesh wire and buffer resources. Thus, optimizing the resources required in the mesh clock synthesis while maintaining the variation tolerance is crucially important. The three major tasks that greatly affect the cost of the resulting clock mesh are: (1) mesh segment allocation , (2) mesh buffer allocation and sizing , and (3) clock sink binding to mesh segments . Previous clock mesh optimization approaches solve the three tasks sequentially, one by one at a time, to manage the runtime complexity of the tasks at the expense of losing the quality of results. However, since the three tasks are tightly interrelated, simultaneously optimizing all three tasks is essential, if the runtime is ever permitted, to synthesize an economical clock mesh network. In this work, we propose an approach that is able to tackle the problem in an integrated fashion by combining the three tasks into an iterative framework of incremental updates and solving them simultaneously to find a globally optimal allocation of mesh resources while taking into account the clock-skew tolerance constraints. The core parts of this work are a precise analysis on the relation among the resource optimization tasks and an establishment of a mechanism for effective and efficient integration of the tasks. In particular, to handle the runtime problem, we propose a set of speedup techniques, that is, modeling the RC circuit for eliminating redundant matrix multiplications, exploiting a sliding-window scheme, and quickly estimating the buffer sizing effect, which are fitted into our context of fast clock-skew estimation in mesh resource optimization as well as an invention of early decision policies. Through extensive experiments with benchmark circuits, it is shown that our proposed clock mesh synthesizer is able to reduce the worst-case clock skew, total mesh wirelength, total size of mesh driving buffers, and total clock mesh power consumption including short-circuit power by 25.0%, 13.2%, 10.9%, and 11.0% on average compared to that produced by the best-known clock mesh synthesis method (MeshWorks), respectively.

A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered one of the most promising non-volatile memory candidates thanks to its excellent performance in terms of access speed, endurance, and compatibility to CMOS. However, high power supply voltage is required in the conventional STT-MRAM writing circuit, which results in high power consumption (e.g., ~10 pJ/bit). In addition, it suffers from stochastic switching behavior and process voltage temperature variations. These make power-efficient and reliable write/read circuits become critical challenges. In this paper, we present novel circuits and architectures to build a 16 kb STT-MRAM design with low power and high reliability. For example, the self-enable switching scheme reduces the power consumption effectively and the fore-placed sense amplifier improves the robustness to process variation. Using an accurate compact model of 65 nm STT-MRAM and a commercial CMOS design kit, mixed transient and statistical simulations have been performed to validate this design.

A gate-delay model focusing on current fluctuation over wide range of process–voltage–temperature variations

This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wide-ranging process–voltage–temperature (PVT) variations. The proposed model translates an output-current fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90- and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in single- and multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well.

A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs

A process, voltage, temperature (PVT) insensitive boosted charge transfer (BCT) circuit for charge-domain (CD) pipelined analog-to-digital converters (ADC) is presented. The output charge of existing BCT varies extensively with PVT variation, leading to large common-mode charge errors in each differential BCT stage when used in CD pipelined ADCs. Therefore, complicate common-mode control circuits must be adopted to stabilize the common-mode charge of each stage, which consumes large power and chip area. The proposed BCT circuit employs a differential difference amplifier and a differential voltage reference to reject the charge errors caused by PVT variations. A 125-MSPS, 10-bit CD pipelined ADC without common-mode control circuit is implemented based on the proposed BCT, consuming only 27mW from a 1.8V supply.

Fast settling frequency synthesizer with two‐point channel control paths

SUMMARYA frequency synthesizer with low‐power and very short settling time is introduced, which utilizes two‐point channel control paths. While the main‐path is the same as normal channel controls, a digital‐to‐analog converter (DAC) with tunable gain is used for the compensation‐path to form a feed‐forward direct voltage‐controlled oscillator (VCO) control path. When the two paths are ideally matched, the two‐point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor‐loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near‐zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase‐locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is − 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd.

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System

Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 μm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500 * 750 μm chip area for the 100―400 MHz measurement range.

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%-76% reduction in 3sigma clock skew value and 84%-88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations.