Process Variations Research Articles

A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations

The physical unclonable function (PUF) is a hardware security primitive that can be used to prevent malicious attacks aimed at obtaining device information at the hardware level. The ring oscillator (RO) PUF has attracted considerable research attention. To improve the reliability of the RO PUF under voltage and temperature changes, the response of the duty-cycle (DC) PUF was obtained by comparing the duty cycle of the RO rather than the period. However, this method reduces the effective utilization of process variations, which limits its implementation in mature advanced manufacturing processes. In this study, a splitting duty-cycle (SDC) PUF was proposed to balance the effective extraction of process variations and robustness under voltage and temperature changes. The sensibility formula between the performance of SDC PUF and process, voltage, and temperature was established through a circuit model and statistical methodology, and the comprehensive characteristics of SDC PUF were analyzed theoretically. Next, 16 SDC PUFs with 128-bit responses were implemented and measured on a Xilinx Virtex-7 device. The experimental results revealed that the average native reliability of SDC PUF was 98.97%, and the reliability was 97.32% under various voltage and temperature conditions. This result revealed advantages over the DC PUF implemented in the same device. The uniqueness of the SDC PUF was 50.42%, and it passed the NIST SP 800-22 randomness and autocorrelation function tests.

Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture

Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

Effect of adaptation gain and reference model in MIT and Lyapunov rule–based model reference adaptive control for first- and second-order systems

An adaptive control law encompasses a regulating control rule compensating for system dynamics variations by adjusting the controller characteristics to maintain the overall system performance. Recently, some techniques have been developed based on fundamental aspects of the adaptability of living organisms. The adaptive control method is a technique that measures the dynamic characteristics of the plant automatically and continuously to make a comparison with its required output. It utilizes the difference between these two to commute adaptable system parameters to maintain optimal performance regardless of the system variations. The behavior of the adaptation rule is significantly affected by the adaptation gain value. Here, it has also been investigated that the adaptation gain range is wide for the systems with the lower order. The appropriate range of adaptation gain decreases as the order of the system increases. In the present work, the model reference adaptive control (MRAC) for first- and second-order systems has been designed and investigated using a wide range of values for the adaptation gain and variations in the reference model parameters. The MIT (Massachusetts Institute of Technology) and Lyapunov rules are applied for the analyses of systems. On the MATLAB/Simulink platform, all the adaptation process comparisons, variations, and investigations have been carried out by altering the adaptation gain and the reference model parameters. The obtained results present encouraging outcomes.

Monitoring Techniques and Performance of Construction Projects in Rwanda. A case of Rehabilitation of Amahoro National Stadium in Gasabo District

This research aimed to evaluate the relationship between monitoring techniques and construction project performance in Rwanda, specifically in the rehabilitation of Amahoro National stadium. The study used a survey method with a well-structured questionnaire, with a sample size of 127 participants. Data was collected using descriptive statistical analysis, inferential statistics, and Pearson correlation (r) and multiple linear regression analysis. Results showed that 66.2% of participants agreed that requirements were well-planned in the rehabilitation of Amahoro National stadium, 89.8% agreed that requirements were communicated correctly, 63.7% agreed that process variation in the rehabilitation was consistent, and 68.5% agreed that project schedule status was continuously reviewed in meetings. Pearson correlation analysis revealed that the Requirement Traceability Matrix, control chart, and status review meeting all had positive and statistically significant relationships with project performance. The multiple regression model was significant, indicating that 57.2% of construction project performance can be attributed to the effectiveness of monitoring techniques used in the project. The researcher concluded that monitoring techniques have a positive effect on the performance of construction projects in Rwanda. To ensure inclusivity in the review process, the researcher recommends using status review meetings as an approach to communicate top-down project needs and reviewing from bottom-up. Customizing control charts to fit the specific project being monitored is highly recommended. For the rehabilitation of Amahoro stadium and other construction projects, owners should be keen to monitor progress to ensure effectiveness in performance. Keywords: Monitoring Techniques, Performance, Construction, Projects, Rwanda

A synergistic chemometric combination for whiteness and greenness assessed HPLC-DAD assay of aqueous extracts of ivy and thyme and potassium sorbate in a syrup formula

A stability-indicating fit-for-purpose method has been developed for co-determination of hederacoside C (HC), thymol (TL), and potassium sorbate (PS) combined in a syrup dosage form. Carvacrol (CL) was separated from thyme extract (THY) with demonstrated identity at high confidence. This method was based on a reversed-phase (RP) high performance liquid chromatographic (HPLC) separation of the cited analytes. The HPLC separation was performed on a RP Zorbax Eclipse XDB-C18 analytical column [250 × 4.6 mm, 5 µm (80 Å)] and SecurityGuard C18 guard column (4 × 3 mm, 5 µm) with gradient elution system of HPLC far UV grade acetonitrile and 20 mM aqueous potassium dihydrogen phosphate buffer adjusted to pH 2.1 as the mobile phase at a flow rate of 2.5 mL min−1 and column oven was set at 50 °C. Quantitation was achieved with the photodiode array detection (DAD) with interferent peak suppression. Target Measurement Uncertainty (TMU) was determined by misclassification rates approach employing 100,000 Monte Carlo simulations (MCS). The bias and imprecision standard deviation were combined as a total analytical error (TAE) and compared via an enhanced approach linked to product specifications, process variation, and shelf-life variability for proving a fit-for-purpose analytical procedure. The robustness of the method was checked using supersaturated design constructed from Plackett-Burman design (PB-SSD) which was statistically analysed via the very recent approach of autovalidation using self-validated ensemble modelling (SVEM). The calibration graphs for each analyte were rectilinear in the range of 42.12–560.00, 3.37–47.15 and 0.51–7.07 µg mL−1 for PS, HC, and TL, respectively. The proposed HPLC-DAD method was successfully applied for the determination of the investigated analytes in a syrup formula. Moreover, the whiteness and greenness of the procedure were assessed via the most recently cited approaches.

A computational modeling approach to investigating mind wandering-related adjustments to gaze behavior during scene viewing

Research on gaze control has long shown that increased visual-cognitive processing demands in scene viewing are associated with longer fixation durations. More recently, though, longer durations have also been linked to mind wandering, a perceptually decoupled state of attention marked by decreased visual-cognitive processing. Toward better understanding the relationship between fixation durations and visual-cognitive processing, we ran simulations using an established random-walk model for saccade timing and programming and assessed which model parameters best predicted modulations in fixation durations associated with mind wandering compared to attentive viewing. Mind wandering-related fixation durations were best described as an increase in the variability of the fixation-generating process, leading to more variable—sometimes very long—durations. In contrast, past research showed that increased processing demands increased the mean duration of the fixation-generating process. The findings thus illustrate that mind wandering and processing demands modulate fixation durations through different mechanisms in scene viewing. This suggests that processing demands cannot be inferred from changes in fixation durations without understanding the underlying mechanism by which these changes were generated.

Resin pressure monitoring method and variation in autoclave processing of polymer composite laminates using capillary sensors

Resin pressure monitoring method and variation in autoclave processing of polymer composite laminates using capillary sensors

Model-free frequency regulation in islanded microgrids: An event-triggered adaptive dynamic programming approach

This paper is concerned with frequency regulation in islanded microgrids via an event-triggered adaptive dynamic programming method. Comparatively to the existing works, we relax the typical limitations on the system, namely, exactly known models, constant load impedances, and single operation mode. The adopted frequency regulation scheme can reach frequency synchronization within the acceptable bounds in the presence of the model uncertainties, operation mode switching, and time-varying loads with no need for any prior information on the system parameters. By employing an event-triggered scheme, the secondary controller is updated only at the aperiodic triggering instants which contributes to less transmission cost. Besides, the use of measurements can help the adaptive weights to be adjusted online in the approximation process, which allows the proposed controller to adapt to the disturbances in real time. Finally, tests including the islanding process and load variation are performed in MATLAB/SimPowerSystem to show the effectiveness of the proposed method.

Robust topology optimization considering part distortion and process variability in additive manufacturing

This paper presents a method to consider uncertainties in the distortion prediction of additive manufacturing processes within robust topology optimization. The random variable of the stochastic additive manufacturing process is the inherent thermomechanical strain, typically determined by process characterization experiments. The value of the inherent strain per se encompasses uncertainty due to differences between characterization and production geometries, uncontrolled process variations, hatching pattern choices, and other effects not captured in layer-by-layer part-scale additive manufacturing simulation. These effects can be represented by different inherent strains for each realized layer, therefore, model the variability in part distortion. Instead of employing a more detailed simulation approach, requiring significantly more process data and computation time, our method aims at generating a robust design in this setting, to obtain parts exhibiting reduced distortion regardless of uncertainties in distortion prediction. The formulation benefits from the superposition potential within the employed process simulation. For robust optimization, the expected part distortion and its estimated variance are included in the standard density-based topology optimization algorithm’s objective function. The effectiveness of the approach is demonstrated by simultaneously optimizing structural performance combined with a minimized additive manufacturing part distortion under uncertain process conditions.

Comparative Study of Photonic Platforms and Devices for On-Chip Sensing

Chemical and biological detection is now an indispensable task in many fields. On-chip refractive index (RI) optical sensing is a good candidate for mass-scale, low-cost sensors with high performance. While most literature works focus on enhancing the sensors’ sensitivity and detection limit, other important parameters that determine the sensor’s yield, reliability, and cost-effectiveness are usually overlooked. In this work, we present a comprehensive study of the different integrated photonic platforms, namely silica, silicon nitride, and silicon. Our study aims to determine the best platform for on-chip RI sensing, taking into consideration the different aspects affecting not only the sensing performance of the sensor, but also the sensor’s reliability and effectiveness. The study indicates the advantages and drawbacks of each platform, serving as a guideline for RI sensing design. Modal analysis is used to determine the sensitivity of the waveguide to medium (analyte) index change, temperature fluctuations, and process variations. The study shows that a silicon platform is the best choice for high medium sensitivity and a small footprint. On the other hand, silica is the best choice for a low-loss, low-noise, and fabrication-tolerant design. The silicon nitride platform is a compromise of both. We then define a figure of merit (FOM) that includes the waveguide sensitivity to the different variations, losses, and footprint to compare the different platforms. The defined FOM shows that silicon is the best candidate for RI sensing. Finally, we compare the optical devices used for RI sensing, interferometers, and resonators. Our analysis shows that resonator-based devices can achieve much better sensing performance and detection range, due to their fine Lorentzian spectrum, with a small footprint. Interferometer based-sensors allow engineering of the sensors’ performance and can also be designed to minimize phase errors, such as temperature and fabrication variations, by careful design of the interferometer waveguides. Our analysis and conclusions are also verified by experimental data from other published work.

Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration

The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature.

Starting from Scratch: A Holistic Framework for Designing Digitally Delivered Graduate Programs for STEM Working Professionals

Provided the opportunity to create new, high-quality graduate programs from scratch, a framework was sought to help meet the intersecting needs of employers and employees, while cultivating a learning environment that honors the individuality of working professionals. Given Rensselaer Polytechnic Institute’s (RPI) nearly 200 years of engineering and research excellence, it was natural to leverage the engineering design process to develop a modern solution. Though there are many variations of the engineering design process, this paper presents it as a sequence of six steps: identify, explore, design, create, test, and improve. The first three steps (identify, explore, and design) are the focus of this work. From these emerged a series of strategic decisions in program logistics (face-to-face, online, hybrid, etc.), curriculum design, and learning interface informed by thorough consideration of employer and employee needs as well as the latest in learning science. Due to the abundance of variety in how graduate programs are designed, this paper provides a detailed description of the design process such that other institutions looking to develop quality, digitally delivered programs, may consider this work. Consequently, clear connections are made between the needs of employers and employees, learning science, and research design. In all, eight graduate certificates, 10 sets of learning goals and competencies (LG&Cs), 25 project-based courses, and more than 60 projects have successfully been designed, developed, and delivered using the described process as a framework for program development. Future papers will explore how these courses and projects were created, tested, and improved through course development and review and revision processes that incorporate regularly cadenced instructor and student feedback.

‘The burden of wanting to make it right’: thematic analysis of semistructured interviews to explore experiences of planning for crisis standards of care and ventilator allocation during the COVID-19 pandemic in the USA

ObjectivesThe COVID-19 pandemic prompted planning for clinical surges and associated resource shortages, particularly of equipment such as ventilators. We sought to examine the experience of the healthcare professionals who created...

Deep-Learning-Based Adaptive Error-Correction Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising emerging non-volatile memory (NVM) technology with wide applications. However, the data recovery of STT-MRAM is affected by the diversity of channel raw bit error rate (BER) across different dies caused by process variations, as well as the unknown resistance offset due to temperature change. Therefore, it is critical to develop effective decoding algorithms of error correction codes for STT-MRAM. In this paper, we first propose a neural bit-flipping (BF) decoding algorithm, which can share the same trellis representation as the state-of-the-art neural decoding algorithms, such as the neural belief propagation (NBP) and neural offset min-sum (NOMS) algorithm. Hence a neural network (NN) decoder with a uniform architecture but different NN parameters can realize all these neural decoding algorithms. Based on such a unified NN decoder architecture, we further propose a novel deep learning (DL)-based adaptive decoding algorithm whose decoding complexity can be adjusted according to the change of the channel conditions of STT-MRAM. Extensive experimental evaluation results demonstrate that the proposed neural decoders can greatly improve the performance over the standard decoders, with similar decoding latency and energy consumption. Moreover, the DL-based adaptive decoder can work well over different channel conditions of STT-MRAM irrespective of the unknown resistance offset, with a 50% reduction of the decoding latency and energy consumption compared to the fixed decoder.

MOSFET only low power sub‐bandgap voltage reference by subtraction of slope compensated proportional‐to‐absolute‐temperature voltage references

SummaryVoltage references are typically designed by combining a complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltage references. However, in contrast to conventional voltage references, the proposed circuit generates a voltage reference by subtracting two PTAT voltages, resulting in an extremely low process‐dependent voltage reference. A novel subtractor is also proposed for subtracting PTAT voltages, which is used to generate the reference voltage. The temperature coefficient of the proposed voltage reference is further improved using a novel PTAT slope compensation technique. The proposed voltage reference is a MOS‐only ultra‐low power circuit that works with sub‐bandgap supply voltage. Simulation results using UMC 0.18 m technology MOSFETs show that the proposed circuit has a line sensitivity of 0.5%/V, a temperature coefficient of 21.37 ppm/° C, a power consumption of 15.6 nW, and an output voltage variation of only 0.22% due to process variations.

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing

As the timing guardband consumes more and more design margin with the technology scaling, better-than-worst-case (BTWC) techniques have gained more attention as a promising solution. BTWC techniques can relax the design margin by transcending the pessimistic static timing constraints and utilizing the dynamic timing information. However, to guarantee the design reliability throughout the lifetime, the conventional dynamic timing analysis (DTA) engines need an extra reliability guardband, which is commonly evaluated under the worst-case corners of aging and variation. This type of guardbanding consumes the precious design margin, thus hindering the efficiency improvement from BTWC techniques. Therefore, in this paper, we propose AVATAR, an aging-and variation-aware dynamic timing analyzer that can perform DTA with the impact of transistor aging and random process variation, including the gate-level aging analysis and random variation model that can accurately calculate cell delay under the impact of transistor aging and random variation, and an event-based DTA algorithm that avoids the pessimistic property of graph-based analysis. We also propose an ML-assisted DTA acceleration flow for the multicycle DTA of homogeneous multicore designs. We present two case studies using AVATAR to show its effectiveness. First, we present an application-based dynamic-voltage-frequency-scaling (DVFS) design methodology based on AVATAR, which can exploit application-level dynamic timing slack (DTS) to improve energy efficiency and performance. The results demonstrate that, compared to the design based on the conventional corner-based DTA, the additional performance improvement of the design based on AVATAR can be up to 14% or the additional power-saving can be up to 20%. Second, we demonstrate using the proposed ML-assisted acceleration flow for reliability-aware deep neural network (DNN) accelerator simulation. We use the proposed flow to estimate the impact of timing errors due to aging and random variation on the inference accuracy of two benchmark DNNs. The results demonstrate that the proposed acceleration flow achieves up to 10W speedup with an average error of less than 2%.

Study of the Reliability for the Leakage Mitigation Methods using FinFETs

Introduction: In the very large-scale integration (VLSI) industry, scaling plays an important role in providing compact size and high-speed digital circuits. The major drawbacks faced by logic circuits are power dissipation and process, voltage, and temperature (PVT) variations. In the VLSI industry, the prediction of variability tolerance capability is mandatory to know the future performance of the circuits. The impact of PVT variation is large in nanoscale logic circuits and it has the power to alter the output characteristics of any logic circuit. The reasons that cause PVT variations are manufacturing defects, environmental conditions, and mishandling issues. Aims and Objective: This paper aims to discuss the process variations and briefly describe the previous work related to variability and various factors involved in PVT simulations. It also provides the idea of Monte-Carlo simulation in the Cadence Virtuoso tool. Methods: In this paper, the impact of PVT variations on different fin-shaped field effect transistor (FinFET) circuits was evaluated using the Cadence Virtuoso tool. Monte-Carlo simulation was performed on various leakage reduction techniques for the domino logic with the help of a multi-gate predictive technology model (PTM) FinFET at a 16nm technology node. Results: The footer-less domino logic (FLDL) circuit is designed and simulated using different leakage reduction techniques for reliability analysis. Conclusion: Cascaded leakage control transistor (CLCT) approach shows 81.75%, 67.83%, and 51.25% less statistical mean value for power dissipation as compared to conventional, on-off logic (ONOFIC), and alternative ONOFIC approaches in the case of FLDL OR2 logic circuit, respectively.

Development of Variable-Line Balancing Chart by Risk Assessment Using Monte Carlo Simulation

Line Balancing Chart is one of the most used lean tools for determining cycle time (CT) and lead time (LT) in the production line processes flow, from raw material input until finished product output. However, for traditional Line Balancing Chart, only the average (mean) CT and LT are considered which causing inconsistent performance of the actual production line throughput rate (productivity). In this study, Variable-Line Balancing Chart (V-LBC) is introduced by considering the dynamic CT and LT in a form of (Minimum, Most Likely (mean), Maximum) for each process involved in the production line. The risk assessment for Value-added (VAA) and non-value added (NVAA) events in the flow are also considered for this V-LBC. A Monte Carlo simulation by using @Risk software is utilized to simulate each process CT distribution capability. As a result, each process in the V-LBC could be represented in horizontal and vertical time variables that involve a variable CT (VAA and NVAA) and risk assessment using Risk Assessment-Failure Mode and Effect Analysis (RA-FMEA) approach. The actual root cause led to the process variation also could be identified more accurately from the V-LBC. Hence the correct action could be taken in order to reduce the variation which indirectly increase the production line productivity.

Sensory processing, emotional and behavioural challenges in children with autism spectrum disorder and attention deficit hyperactive disorder

Background Previous studies have found sensory processing abnormalities, behavioural, and emotional challenges in children with developmental disorders, particularly autism spectrum disorder (ASD) and attention deficit hyperactivity disorder. There is little research on the sensory, emotional, and behavioural differences between individuals with autism spectrum disorder and attention-deficit/hyperactivity disorder (ADHD) across age cohorts. Aim This study examined the correlation and differences in sensory processing, emotional, and behavioural challenges in children with autism spectrum disorder, attention-deficit/hyperactivity disorder (ADHD), and typically developing children. This study also examined these characteristics in two age groups: 4–11-year-olds and 12–18-year-olds. Methodology The study included 362 mothers of their children among three groups: 123 with ASD, 100 with ADHD, and 139 from the typical population. The Short Sensory Profile (SSP) and Child Behaviour Checklist were administered to participants along with a demographic profile. The participants were between 25–50. Pearson correlation, MANOVA and MANCOVA were used to fulfil research objectives. Results and discussion The study found a link between tactile sensitivity, sensation seeking, auditory filtering, and behavioural and emotional issues in children with ASD and ADHD. Sensory features also predicted emotional and behavioural issues in these populations. The MANCOVA analysis showed significant variations in sensory processing, behavioural, and emotional issues among populations, controlling for age groups. Conclusion In conclusion, this study shows the need for early diagnosis of sensory processing impairments in these groups and developmental-stage-specific therapies. The study highlights the need for longitudinal research to understand sensory processing patterns, emotional, and behavioural issues, and development, particularly in India.