Printed Circuit Board Design Research Articles

On the Modeling, Characterization, and Analysis of the Current Distribution in PCB Transmission Lines With Surface Finishes

Due to manufacturing requirements, surface finishes have become a necessity in printed circuit board design. These finishes have significant effects on the RF performance of the transmission lines. In this paper, a filament modeling approach is used to model skin, proximity, and surface roughness effects in transmission lines with surface finishes up to 70 GHz. The approach shows a high accuracy compared with measurements. The model also gives an insight into how the current distributes itself by showing the frequency dependent proportion of the current that flows in each surface finish layer. In the case of NiP–Au or Ni–Au surface finishes, current migrates increasingly into gold at high frequencies and reaches a maximum in the Ni or NiP at around 3.5 GHz, and then declines. The distribution of the current in different materials can also be explained as the decay of an electromagnetic wave at the surface of the conductor. This approach shows that the evanescent wave in the cross section of the conductor can be analyzed as analog to a transmission–reflection problem, what we will call the surface finish effect. This effect brings into question the accuracy of the traditional skin-depth value, $\delta $ , and the models that depend on it, such as most surface roughness correction factors, for structures where different metals are layered in thicknesses that are not much larger than $\delta $ .

Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs

It is known that bus-oriented escape routing and area routing are necessary in a high-speed printed circuit board (PCB) design. In this paper, given a set of global routed buses in a high-speed PCB design, it is assumed that the routed nets in a single bus are represented as a bus-oriented net between two escaped boundary pins. Based on the construction of a virtual wall between two circuit components, the connection transformation of the given bus-oriented nets inside a closed region and the construction of a covering graph for the represented intervals, an iterative modified left-edge algorithm is proposed to minimize the number of the assigned layers and assign all the bus-oriented nets onto the available layers. Compared with Tsai’s algorithm, the experimental results show that our proposed algorithm reduces 15.0% of the layer number and 21.9% of CPU time for six tested examples on the average, respectively. Compared with Chin’s algorithm, the experimental results show that our proposed algorithm use less CPU time to reduce 15.0% of the layer number for six tested examples on the average.

Revisiting the Effect of Nickel Characteristics on High-Speed Interconnect Performance

It has been observed that some surface finish like nickel–gold plating has exhibited significantly higher losses than expected on high-speed interconnects like printed circuit board (PCB) trace and packaging. The investigation has revealed that this extra loss results from the ferromagnetic characteristics of nickel material with large resistivity and nonunit frequency-dependent relative permeability. As a result, a high-speed PCB design must take into account the board surface finish effect, solder-mask coating, and the physical geometry deformation of copper related to the etching process when modeling the PCB trace, which can be accomplished by using 3-D electromagnetic field simulation tools. Simulation results are correlated with vector network analyzer (VNA) measurements on several test cases and also on the actual application boards. In our experimental studies on PCB test structures with electroless nickel/immersion-gold (ENIG) and electroplated nickel–gold plating, there is no observation of resonating anomalies in the insertion loss and group delay related to nickel permeability. Both simulation and measurement results have demonstrated that PCB board with ENIG and solder mask over bare copper finish has less signal loss than that with ENIG or hard-gold finish.

Simultaneous Escape Routing using Network Flow Optimization

With the advancement in technology, the size of electronic components and printed circuit boards (PCB) is becoming small while the pin count of each component is increasing. This has necessitated the use of ball grid array (BGA) type of components where pins are attached under the body of component as a grid. The problem of routing pins from under the body of component to the boundary of the component is known as escape routing. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant PCB design. The task of SER is non-trivial, given the small size of components and hundreds of pins arranged in random order in each component that needs ordered connectivity. In this paper, first we propose flow models for different inter pin capacities. We then propose linear network flow optimization model that simultaneously solves the net ordering and net escape problem. The model routes maximum possible nets between two components of the PCB, by considering the design rules. Comparative analysis shows that the proposed optimization model performs better than the existing routing algorithms in terms of number of nets routed.

Quality Control of PCB using Image Processing

An automated testing system for Printed Circuit Board (PCB) is preferred to get the technological advances in PCBs design and manufacturing, eliminates particular aspects and then provides fast, quantitative, and dimensional impositions. It reduces the testing time and manufacturing cost as human inspectors decisions are ineffective, slow and costly. Thus in this area, digital image processing can be used mainly for the detection of faulty parts or missing components. This system mainly deals with analysis to detect faulty PCB. Digital camera is used in automated visual inspection system that captures image of each sample PCB product. The captured image is then provided to computer for further processing which includes conversion in various forms such as Gray scale image and binarized image. XOR operation is performed on these converted images to obtain the required results. Contour Analysis is performed on these results for classification. Missing components, polarities, circuit breaks, missing tracks these types of faults are detected and classified accordingly. This concept increases the speed and accuracy, eliminates human errors which are frequent in quality testing and also overcomes the weakness in the existing system. Hence the productivity can be increased by replacing manual testing with the proposed concept. General Terms Image Processing, Quality Control, Printed Circuit Board.

Numerical simulation of the electrical performance of printed circuit boards under cyclic thermal loads

Different Printed Circuit Board (PCB) designs were tested in an Interconnection Stress Test. In such a test, PCBs were subjected to temperature cycles alternating between two extremes (e.g. −40°C to 160°C). The electrical resistance was measured on-line during these tests. If the resistance rose by more than 10% of the initial value at the highest temperature, the test was terminated. The PCB structures were modeled by means of the Finite Element Analysis (FEA) Software Abaqus using a viscoplastic material model extended by a mean backstress memorization for the domain representing the copper interconnections. The stress/strain states computed by Abaqus served as input to a pore growth model which eventually allowed working out an indicator for the electrical performance loss. Subsequently, electrical FEA were conducted to obtain a correlation between the pore volume fraction distributed over the structure and the electrical resistance increase. The results of the simulations were compared to experimental results to determine parameters for the pore growth model. A well calibrated pore fraction evolution law allowed reliably predicting the electrical performance of various PCB designs as well as drawing some conclusions on the initial pore volume fraction in the PCB prior to operation.

An evolutionary design methodology of printed circuit boards for high-speed VLSIs

As operation frequencies of the printed circuit boards (PCBs) increase in keeping with VLSI frequencies in the GHz domain, two independent serious problems occur in the PCB design. One is waveform distortion problem, or signal integrity (SI) degradation problem, in PCB traces. And the other is power-supply drop problem, or power integrity (PI) degradation problem, in PCB power planes. Those problems are barely able to be overcome on case-by-case empirical designs conventionally. In this paper we newly propose a design approach for each problem, both of which are based on the genetic algorithm. And we obtained improvement ratios of more than double compared with the both conventional designs for SI and PI degradations, respectively.

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs

Pin assignment and escape routing are two closely related problems and it is desired to consider routability during pin assignment for package-board co-design. During pin assignment and escape routing, differential pairs and blind-via usage are two major factors to be considered in modern printed circuit board designs. However, most previous works only target on either differential pairs or blind-via usage but cannot handle both of them simultaneously. In this paper, we propose the first package-board co-design method to optimize the pin assignment and escape routing in the presence of differential pairs and blind-via usage for grid pin array. Experimental results show that our package-board co-design flow can achieve wirelength improvement and reduce the number of layers required compared with competitive baseline flows.

A Wireless Optogenetic Headstage with Multichannel Electrophysiological Recording Capability.

We present a small and lightweight fully wireless optogenetic headstage capable of optical neural stimulation and electrophysiological recording. The headstage is suitable for conducting experiments with small transgenic rodents, and features two implantable fiber-coupled light-emitting diode (LED) and two electrophysiological recording channels. This system is powered by a small lithium-ion battery and is entirely built using low-cost commercial off-the-shelf components for better flexibility, reduced development time and lower cost. Light stimulation uses customizable stimulation patterns of varying frequency and duty cycle. The optical power that is sourced from the LED is delivered to target light-sensitive neurons using implantable optical fibers, which provide a measured optical power density of 70 mW/mm2 at the tip. The headstage is using a novel foldable rigid-flex printed circuit board design, which results into a lightweight and compact device. Recording experiments performed in the cerebral cortex of transgenic ChR2 mice under anesthetized conditions show that the proposed headstage can trigger neuronal activity using optical stimulation, while recording microvolt amplitude electrophysiological signals.

Realistic warpage evaluation of printed board assembly during reflow process

Purpose – This paper aims to develop an estimation tool for warpage behavior of slim printed circuit board (PCB) array while soldering with electronic components by using finite element method. One of the essential requirements for handheld devices, such as smart phone, digital camera, and Note-PC, is the slim design to satisfy the customers’ desires. Accordingly, the printed circuit board (PCB) should be also thinner for a slim appearance, which would result in decreasing the PCB’s bending stiffness. This means that PCB deforms severely during the reflow (soldering) process where the peak temperature goes up to 250°C. Therefore, it is important to estimate PCB deformation at a high temperature for thermo-mechanical quality/reliability after reflow process. Design/methodology/approach – A numerical simulation technique was devised and customized to accurately estimate the behavior of a thin printed board assembly (PBA) during reflow by considering all components, including PCB, microelectronic packages and solder interconnects. Findings – By applying appropriate constraints and boundary conditions, it was found that PBA’s warpage can be accurately predicted during the reflow process. The results were also validated by warpage measurement, which showed a fairly good agreement with one and another. Research limitations/implications – For research limitations, there are many assumptions regarding numerical modeling. That is, the viscoplastic material property of solder ball is ignored, the reflow profile is simplified and the accurate heat capacity is not considered. Furthermore, the residual stress within the PCB, generated at PCB manufacturing process, is not included in this paper. Practical implications – This paper shows how to calculate PBA warpage during the reflow process as accurately as possible. This methodology helps a PCB designer and surface-mount technology (SMT) process manager to predict a PBA warpage issue and modify PCB design before PCB real fabrication. Practically, this modeling and simulation process can be easily performed by using a graphical user interface (GUI) module, so that the engineer can handle an issue by inputting some numbers and clicking some buttons. Social implications – In a common sense manner, a numerical simulation method can decrease time and cost in manufacturing real samples. This PCB warpage method can also decrease product development duration and produce a new product earlier. Furthermore, PCB is a common component in all the electronic devices. So, this PCB warpage method can have various applications. Originality/value – Because of an economic advantage, the development of a numerical simulation tool for estimating the thin PBA warpage behaviour during reflow process was attempted. The developed tool contains the features of detailed modeling for electronic components and contact boundary conditions of the supporting rails in the reflow oven.

Optimizing power converter PCB design for lower EMI

Purpose – The purpose of this paper is to develop a novel technique for the pre-design of a printed circuit board (PCB) of a DC-DC power converters where the placement of electric components can cancel the electromagnetic emissions through subtractive coupling and in this sense to minimize the stray magnetic and electric fields at a specific location. For this work the location of interest is a current transducer used for control purposes positioned in the center of a DC-DC Cuk converter board as a constrain. Design/methodology/approach – The methodology of design is based on the development of an interface software platform through MatLab script coding which interconnects the solution of a numerical analysis software and an optimization technique. The numerical analysis software is based on finite element calculations where quasi-static field analysis are performed to calculate the radiated electric and magnetic fields. The optimization technique is conducted by genetic algorithms (GAs). Findings – The r...

Influence of the cavities on the PCB mechanical properties

Purpose – The main aim of this paper is to investigate the influence of the cavity coverage on the printed circuit boards (PCB) to the resonant frequency, acceleration and displacement. Design/methodology/approach – Tests were realized on four PCBs with different cavity areas. Frequency range of tests was between 10 and 2,000 Hz with 0.3 g acceleration amplitude. In addition, more simulations were performed to check different setups of the boards. Findings – From the calculated and measured data, it is clear that with the larger cavity area the resonance frequency drops. In case a greater number of components placed in cavities are needed on board, it is appropriate to use multiple smaller cavities than the bigger ones. Originality/value – Results in this paper could be very useful for PCB manufacturers and designers during designing of the new PCBs with cavities for dipped components.

How Secure Are Printed Circuit Boards Against Trojan Attacks?

Hardware Trojan attacks at the integrated circuit (IC) level have been studied extensively in recent times. Researchers have analyzed the impact of these attacks and explored possible countermeasures for ICs. However, vulnerability with respect to hardware Trojan attacks at higher levels of system abstraction, e.g., at printed circuit board (PCB) level, have not been reported earlier. Previous studies have covered security of PCBs against piracy and various post-fabrication tampering attacks. JTAG (Joint Test Access Group) and other field programmability features, e.g., probe pins, unused sockets and USB have been extensively exploited by hackers to gain access to internal features of the designs as well as snooping of secret key, collection of test responses, and manipulating JTAG test pins. One instance demonstrated that Xbox can be hacked by disabling the Digital Rights Management (DRM) policy using JTAG. The emerging business model of PCB design and fabrication that favors extensive outsourcing and integration of untrusted components/entities in the PCB life-cycle to lower manufacturing cost, makes hardware Trojan attacks in PCBs highly feasible.

Thermal fluid-structure interaction of PCB configurations during the wave soldering process

Purpose – This paper aims to investigate the thermal fluid–structure interactions (FSIs) of printed circuit boards (PCBs) at different component configurations during the wave soldering process and experimental validation. Design/methodology/approach – The thermally induced displacement and stress on the PCB and its components are the foci of this study. Finite volume solver FLUENT and finite element solver ABAQUS, coupled with a mesh-based parallel code coupling interface, were utilized to perform the analysis. A sound card PCB (138 × 85 × 1.5 mm3), consisting of a transistor, diode, capacitor, connector and integrated circuit package, was built and meshed by using computational fluid dynamics pre-processing software. The volume of fluid technique with the second-order upwind scheme was applied to track the molten solder. C language was utilized to write the user-defined functions of the thermal profile. The structural solver analyzed the temperature distribution, displacement and stress of the PCB and its components. The predicted temperature was validated by the experimental results. Findings – Different PCB component configurations resulted in different temperature distributions, thermally induced stresses and displacements to the PCB and its components. Results show that PCB component configurations significantly influence the PCB and yield unfavorable deformation and stress. Practical implications – This study provides PCB designers with a profound understanding of the thermal FSI phenomenon of the process control during wave soldering in the microelectronics industry. Originality/value – This study provides useful guidelines and references by extending the understanding on the thermal FSI behavior of molten solder for PCBs. This study also explores the behaviors and influences of PCB components at different configurations during the wave soldering process.

THE Age of DIY and Dawn of the Maker Movement

HELLO, WORLD! We live in interesting times. While people have been “making” things for quite a while, the last few years has seen the emergence of a distinctive maker and DIY (“do-it-yourself ”) culture all around the world. One interesting facet of the maker culture is its pervasiveness. One does not need a PhD or professional license to be a part of this culture. It is pop culture at its finest! The cost of building a small, interesting robot today is really only a few hundred US dollars. A decent 3D printer can be built for under five hundred (not including ink). There are reasonable digital oscilloscopes that fit inside a watch or plug inside your PC. The precipitous drop in cost of materials and equipment, along with the widespread dissemination of knowledge via low barrier mediums like online videos and the web have all had a hand in making “DIY” easier than ever before. At the heart of the maker world is a collaborative community spirit, whether it is about sharing designs, working collaboratively in a shared space (a.k.a. “hackerspaces”), raising funds from a broad community of interest, or showing off your cool project at venues such as Makerfaire. The community of makers utilizes traditional manufacturing techniques (e.g., woodand metal-working). The special twist is that one does not need to go through an apprenticeship process and commit to years of study along with a vocation. Rather, one can simply find the closest hackerspace and join up or organize a course on PCB (“Printed Circuit Board”) design, soldering, or forging pendants by melting discarded coke cans. In addition, there are some enabling technologies – single board microcontrollers and 3D printers that became popular among the hobbyist communities over the last few years. These are distinct faces of the maker community. Finally, there are a plethora of applications that the maker community is interested in. This changes over time but recently, there is great interest in small robots, flying drones and quantifying one’s daily routines and habits. In this piece, we’ll be exploring some of these broad trends.

Three-Dimensional Cylindrical Model for Single-Row Dynamic Routing

Single-row routing is a technique to route pairs of pins aligned in a single axis into non-crossing nets to form a least congested network. The technique has its main application in the printed circuit board design where the nets between the pins are drawn statically, that is, in a fixed manner. In the dynamic single-row routing, the nets from the pairs of pins in the network are allowed to change according to the requirement. This paper proposes a new dynamic single-row routing model for the switching of pins based on the cylindrical design. In the model, a cylinder has unlimited number of planes that are formed by traversing its circular cross-section. Each plane houses a network of single-row pins that share the same pins. As the planes do not overlap, the nets in the networks do not cross as they are placed in different planes. This makes it possible to allow the configuration of the nets to change according to pin connection requirements for forming the dynamic model. The single-row routings in each network are produced optimally using our earlier model called ESSR (Enhanced Simulated annealing for Single-row Routing). This suggests that the cylindrical model is optimal and suitable for adoption into problems requiring massive pin connections such as in switching. Keywords: Single-row Routing; Dynamic Configuration; ESSR; Induction formula. 2010 Mathematics Subject Classification:

An Experimental Approach for Locating the Current Distribution in Multiphase Buck Converters

The objective of this paper is to present a methodology for identifying the current flow in the capacitors of a multiphase buck converter by synchronously measuring the capacitor currents. A multiphase buck converter uses multiple parallel buck converters with different switching times to source a large amount of current. Currents in the primary capacitors of a multiphase buck converter are drawn by all phases of the converter; however, the phases switch asynchronously. Synchronizing to the switching of a specific phase reveals how the current from that phase is distributed among the capacitors throughout a circuit board. The proposed measurement method is illustrated by comparing an initial printed circuit board design to a new design to show the effect of better capacitor placement and the addition of a ground plane. The new design confines the phase currents to the capacitors close to the field effect transistors of the specific phase.

Thermal warpage analysis of PBGA mounted on PCB during reflow process by FEM and experimental measurement

Purpose – The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process. Design/methodology/approach – A thermal-mechanical coupling method that used finite-element method software (ANSYS 13.1) was performed. Meanwhile, a shadow moiré apparatus (TherMoiré PS200) combined with a heating platform was used for the experimental measurement of the warpage of PBGA according to the JEDEC Standard. Findings – The authors found that the temperature profiles taken from the simulated results and experimental measurement are consistent with each other, only with a little and acceptable difference in the maximum temperatures. Furthermore, the maximum warpage measurements during the reflow process are 0.157 mm and 0.149 mm for simulation and experimental measurements, respectively, with a small 5.37 per cent difference. The experimental measurement and simulated results are well correlated. Based on the validated finite element model, two factors, namely, the thickness and dimension of PCB, are explored about their effect on the thermal warpage of PBGA mounted on PCB during the reflow process. Practical implications – The paper provides a thorough parametrical study of the thermal warpage of PBGA mounted on PCB during the reflow process. Originality/value – The findings in this paper illustrate methods of warpage study by combination of thermal-mechanical finite element simulation and experimental measurement, which can provide good guidelines of the PCB design in the perspective of thermal warpage during the reflow process.

A fuzzy based self-check capable computerized MCDM aid tool

Purpose – The purpose of this paper is to determine as to develop a fuzzy multi-criteria decision-making (MCDM) algorithm with self-check capability that can solve any manufacturing company's printed circuit boards (PCB) design computer aided design (CAD) tool selection problem and to implement it. Design/methodology/approach – An algorithm that consists of two sub-algorithms that use same inputs and alternative pool is developed, thus self-check capability is introduced. The first sub-algorithm designed as an integration of fuzzy AHP and TOPSIS, where the second sub-algorithm composes of fuzzy analytic network process and TOPSIS. Fuzzy set theory and linguistic variables were utilized to handle uncertainty and usage of verbal expressions, respectively. MATLAB programming language was used for the implementation. The used MCDM methods’ and fuzzy set theory's explanations are given along with the literature review prior to real life application of the developed algorithm. Findings – A MCDM algorithm with self-check capability is introduced. Moreover, a practical decision aid tool is generated for the usage of the manufacturing companies that are related with PCB design. Practical implications – A practical computerized MCDM aid tool is generated. Using the tool let the manufacturers, i.e. high-tech device manufacturers, evaluate available PCB CAD design tools with respect to tangible and intangible criteria, and obtain a reliable result. Originality/value – Self-check capability is incorporated into the decision process. Along with this capability, although the decision-making process takes place in a fuzzy environment, result of the algorithm becomes more reliable than the ones deprived of this characteristic. Furthermore, a practical computerized MCDM aid tool is generated.

Understanding the Effect of PCB Layout on Circuit Performance in a High-Frequency Gallium-Nitride-Based Point of Load Converter

The introduction of enhancement-mode gallium-nitride-based power devices such as the eGaN FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the printed circuit board (PCB) layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET-based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This paper will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design, providing a 40% decrease in parasitic inductance over the best conventional PCB design.