Numerical simulation of the electrical performance of printed circuit boards under cyclic thermal loads

Abstract

Different Printed Circuit Board (PCB) designs were tested in an Interconnection Stress Test. In such a test, PCBs were subjected to temperature cycles alternating between two extremes (e.g. −40°C to 160°C). The electrical resistance was measured on-line during these tests. If the resistance rose by more than 10% of the initial value at the highest temperature, the test was terminated. The PCB structures were modeled by means of the Finite Element Analysis (FEA) Software Abaqus using a viscoplastic material model extended by a mean backstress memorization for the domain representing the copper interconnections. The stress/strain states computed by Abaqus served as input to a pore growth model which eventually allowed working out an indicator for the electrical performance loss. Subsequently, electrical FEA were conducted to obtain a correlation between the pore volume fraction distributed over the structure and the electrical resistance increase. The results of the simulations were compared to experimental results to determine parameters for the pore growth model. A well calibrated pore fraction evolution law allowed reliably predicting the electrical performance of various PCB designs as well as drawing some conclusions on the initial pore volume fraction in the PCB prior to operation.