Enhanced Board Level Design Methodology by Statistical Analysis

Abstract

Today’s server system design becomes more and more challenging and complex due to the data speed of high-speed (HS) input/output (I/O) interfaces increases dramatically. PCI Express Gen4 16Gbps or other CPU to CPU interface with similar data speed is commonly used in the server product motherboard design. The printed-circuit board (PCB) routing maximum length is sometimes limited by these highspeed I/O interfaces. Traditional FR4 PCB material design can’t meet the design target or criteria of these high-speed I/O interfaces. PCB designer need to spend more time in studying different PCB material which can meet their product’s demand. Channel insertion loss (IL) of a motherboard design becomes a dominant factor for the signaling performance of these high-speed I/O interfaces. It is also used by a PCB designer to select the PCB material. But to select a perfect PCB material for a specific design is not easy (or say impossible) for a PCB designer. An improper selection of PCB material may lead to either a costly over design or an increased risk of platform performance. So how to select a cost-effective PCB material for a specific design is an important subject for a PCB designer. Nowadays, some well-developed PCB insertion loss electrical characterization methods like semi-automation Delta-L solution [2] [3] [4] [5] [6] or In-board characterization method$\dots$ etc. have introduced to industrial PCB designers and started to support for the insertion loss measurement of motherboard design. With rigorous and well-defined de-embedding methods, probes footprint designs$\dots$ etc, PCB designer can get insertion loss values of their motherboard design accurately and efficiently. But even though PCB designer can get insertion loss measurement data of their motherboard design accurately, they still can’t do the risk assessment precisely if they don’t have the channel loss specification. In fact, some industry specifications of high-speed I/O interfaces (like PCI Express) have defined the channel insertion loss specification. But the insertion loss value is just a base line. Many silicon design’s companies which products have better signal quality performance. Their products’ equalizer can compensate more channel loss than the base line value. If a PCB designer uses the channel loss value defined in the industry specification as a criterion, then its product is highly possible a costly over design product. To have better solution of this problem, statistical analysis method in getting channel loss criteria is introduced in this paper. DOE/RSM/UPM signal integrity simulation methodology is very popular in the server motherboard design. Sometimes, this simulation method will include silicon transmitter (TX) and receiver (RX) buffer and package variables, channel variables (like PCB trace impedance and length$\dots$ etc.). By removing silicon TX/RX buffer and package variables, channel loss specification can be deduced precisely by using DOE/RSM/UPM simulation method with maximum routing length defined in the platform design guidelines. This criterion is also relatively suitable for a PCB designer to do a cost-effective product comparing with using industry base line criteria.