Logic Primitives Research Articles

Design of robustly testable combinational logic circuits

An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optoelectronic multiple-valued logic implementation

A design for optoelectronic multiple-value logic circuits that uses bistable laser diodes or light-emitting diodes is reported. In this multiple-valued logic design, an optoelectronic tristable switching circuit, or light-current mirror, in which two bistable light-emitting diodes are connected in parallel serves as the basic logic element. Five ternary logic implementations: Complement. Max(x, y), Min(x, y), Cycle, and Literals, have been demonstrated experimentally. Furthermore, any ternary logic function can be generated with the light-current mirror and the logic primitives.

The Place of Logical Primitives in Cognition

The Place of Logical Primitives in Cognition

4740970 Integrated circuit arrangement

The primitive logic functions NOT, AND, OR, NAND, NOR, XOR, and XNOR can be connected together to build slightly more complex functions. A single signal carrying one bit of binary data is known as a scalar entity. A set of signals carrying similar data can be gathered together into a group known as a vector. A key advantage of vector notation is that it allows all of the signals comprising the vector to be easily referenced in a single statement. A multiplexer uses a binary value, or address, to select between a number of inputs and to convey the data from the selected input to the output. A decoder uses a binary value, or address, to select between a number of outputs and to assert the selected output by placing it in its active state. There is a special category of gates called tri-state functions whose outputs can adopt three states: 0, 1, and Z. The tri-state buffer’s symbol is based on a standard buffer with an additional control input known as the enable. A more sophisticated function called a D-type latch can be constructed by attaching two AND gates and a NOT gate to the front of an RS latch. In the case of a D-type flip-flop, the data appears to be loaded when a transition, or edge, occurs on the clock input, which is therefore said to be edge-sensitive. Counter functions are also commonly used in digital systems. The number of states that the counter will sequence through before returning to its original value is called the modulus of the counter.

Correspondence: Genetic epistemology of intelligent natural systems

AbstractGeneral systems theory requires that system properties be distributed. In the cognitive domain, intelligence is a concept that characterizes cognitive behavior. Through philosophical analysis, the systemic distribution of artificial and natural intelligence are evaluated with respect to logical primitives in pattern recognition (qualitative intelligence). In order to determine the extent of that distribution, relevant cognitive conditions in machine programs, infrahumans and humans are examined. Qualitative intelligence is shown to be distributed in infrahuman and human systems but not in machine systems.

The Pions Graphics System

During 1979, CERN began to evaluate how interactive computer graphics displays could aid the analysis of high-energy physics experiments at the new Super Proton Synchrotron collider. This work led to PIONS, a 3D graphics system, which features the ability to store and view hierarchical graphics structures in a directed-acyclic-graph database. It is possible to change the attributes of these structures by making selections on nongraphical information also stored in the database. PIONS is implemented as an object-oriented message-passing system based on Small Talk design principles. It supports multiple viewing transformations, logical input devices, and 2D and 3D primitives. The design allows full use to be made of display hardware that provides dynamic 3D picture transformation.

An interactive system for VLSI chip physical design

The Federal Systems Division has developed a structured design methodology and a companion chip physical design system that has been used to build seven large VLSI chips (ranging in size from 7K to 36K logic primitives). Using the MVISA system, a logic designer has complete control and responsibility for the total chip design. Our experience has been that when this highly interactive software and methodology is used, chip physical design requires less than two weeks. This is a significant savings in design time; but more importantly the designer can allocate more schedule for logic design and simulation. This paper describes how FSD's unique interactive physical design system has improved productivity of VLSI design.

Specification of Synchronizing Processes

The formalism of temporal logic has been suggested to be an appropriate tool for expressing the semantics of concurrent programs. This paper is concerned with the application of temporal logic to the specification of factors affecting the synchronization of concurrent processes. Towards this end, we first introduce a model for synchronization and axiomatize its behavior. SYSL, a very high-level language for specifying synchronization properties, is then described. It is designed using the primitives of temporal logic and features constructs to express properties that affect synchronization in a fairly natural and modular fashion. Since the statements in the language have intuitive interpretations, specifications are humanly readable. In addition, since they possess appropriate formal semantics, unambiguous specifications result.

Fully Digit On-Line Networks

Research in computer architecture in the last decade has been driven largely by the motivation to overcome the von Neumann bottleneck. This paper describes the design and use of one such architecture—fully digit on-line networks. First, digit on-line algorithms and processing are defined. The key advantage to digit on-line processing is that it allows a digit serial, most significant digit first, type of data flow. Processing of the most significant operand digits starts immediately and generation of the most significant result digits soon follows. The minimum set of primitive logic operations required to implement a digit on-line processing component in VLSI are outlined. Then, digit on-line networks consisting of many of these digit on-line components are examined. Finally, two different network configurations are discussed and compared.

First-order logic based on inclusion and abstraction

Quine has shown that set theory may be based on inclusion and abstraction [1937], [1953]. He quantifies over (or abstracts upon) sets of all kinds, of course, including sets of sets. Here I confine Quine's approach to quantification over (abstraction upon) individuals alone, or at any rate their unit classes. Forsaking quantification over sets undercuts Quine's definition of negation, however. Smullyan sketches a first-order restriction of Quine's approach with no bound class variables for which inclusion and abstraction alone are adequate logical primitives [1957, n. 10]. However, the definition of negation requires more than one element in the universe of discourse. This requirement is met for Smullyan because he is doing arithmetic. Here, on the other hand, I presuppose only that the universe is nonempty. Accordingly, I assume a third primitive notion, the empty class. I will show that this threefold basis suffices both for classical first-order logic and for a version of “free” many-sorted logic. The monadic fragment, which I call Boolean logic with abstraction, is intermediate in strength between Boolean class logic and Lesniewski's Ontology. It affords a novel perspective on descriptions, particularly in their generic use.

On the Design of Three-Valued Asynchronous Modules

The use of three-valued signals in the design of asynchronous speed-independent modules is considered. The three-valued Post algebra is used as the mathematical basis for multivalued logic design. Asynchronous operation in a three-valued system is defined. Basis data/control signal detectors and control primitives are developed. It is shown that the design of the nonbinary modules only requires the use of standard binary design techniques and the detectors and logic primitives that are developed. A general monitoring and control structure that allows the interconnection of both combinational and sequential modules is described.

The Complexity of Computational Circuits Versus Radix

The complexity of computational circuits versus radix is analyzed. Necessary and sufficient conditions are given that ensure that the complexity of certain computational circuits will be a monotonically decreasing function of radix. Mechanizations of a higher radix ripple carry adder, look-ahead adder, magnitude comparator, and parallel multiplier are given. Each mechanization is implemented using both I2L threshold logic and standard multiple-valued logic primitives and then tested against the necessary and sufficient conditions previously developed. A comparison is made of the relative effectiveness of I2L threshold logic versus logic primitives in realizing computational circuits whose complexity is a decreasing function of radix.

Functional Level Primitives in Test Generation

This paper deals with the use and development of high-level (functional) primitive logic elements for use in a system which automatically generates tests for complex sequential circuits. The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented. Functional test generation models for two basic elements, a shift register and a counter, are derived, including procedures for implication, D-drive and line justification. Primitive algorithms which generate single as well as multivector (sequences) solutions to D-drive and line justification problems are presented.

Some New Types of Logical Completeness

In this paper, we consider the problem of determining if a given set of simple combinational functions, called logic primitives, can be used to realize any arbitrarily complex combinational function. The complex combinational function is realized by suitably interconnecting the primitives, and in most cases several copies of the primitives. Such a set of primitives is said to be complete in some sense. Two important types of logical completeness that have been previously studied are: 1) strong completeness where the circuit inputs are the uncomplemented variables x1,x2,···,xn, and 2) weak completeness where the circuit inputs are 0,1,x1,x2,···,xn. In this paper, we discuss two new types of logical completeness: strong c-completeness with inputs x1, x1, x2, x2,···,xn, xn and weak c-completeness with inputs 1, 0, x1, x1, x2, x2,···, xn, xn, and we derive necessary and sufficient conditions for a set of primitives to be strong c-complete or weak c-complete. We also discuss the relations between the above four types of completeness. Finally, we consider two more types, complement completeness and dual completeness, which may have applications to some recent technologies.

On Reducibility of Provability in the Primitive Logic [LO

In the present paper, we would like to show a theorem concerning with reducibility of provability in the primitive logic. This theorem seems to suggest a procedure to find the proof-note of a given proposition which is provable in the primitive logic.

Some Remarks on Evaluations of the Primitive Logic

In [4], K. Ono introduced the notion of evaluations of the primitive logic LO and proved that any semi-evaluation E is an evaluation of LO if E satisfies the following conditions: (E1) p* → 0 = 0,(E2) p* → p* = 0,(E3) 0 → p* = p*,(E4) p* → (p* → q*) = p* → q*,(E5) p* → (q* → r*) = q* → (p* → r*),(E6) p* → q* = 0 implies (r* → p*) → (r* → q*) = 0,(E7) (x)p*(x) → p*(t) = 0 for any t, and(E8) if u* → p*(t) = 0 for any t, then u* → (x)p*(x) = 0.

H. H. LoomsJr. , and R. H. WymanJr. , On complete sets of logic primitives. IEEE transactions on electronic computers, vol. EC-14 (1965), pp. 173–174.

H. H. LoomsJr. , and R. H. WymanJr. , On complete sets of logic primitives. IEEE transactions on electronic computers, vol. EC-14 (1965), pp. 173–174.

H. H. LoomsJr., and R. H. WymanJr., On complete sets of logic primitives. IEEE transactions on electronic computers, vol. EC-14 (1965), pp. 173–174.

H. H. LoomsJr., and R. H. WymanJr., On complete sets of logic primitives. IEEE transactions on electronic computers, vol. EC-14 (1965), pp. 173–174.

On a class of set-theoretical interpretations of the primitive logic

On a class of set-theoretical interpretations of the primitive logic

A Study on Formal Deductions in the Primitive Logic

Main purpose of the present paper is to study formal deductions described along the line of my former work [1]. In the present paper, I restrict myself to the primitive logic. To extend this method to other logics such as the lower classical predicate logic or the intuitionistic predicaste logic, my way of practical discription has to undergo a certain extent of modification.