Presence Of Process Variations Research Articles

A Flexible and Reliable RRAM-Based In-Memory Computing Architecture for Data-Intensive Applications

This paper proposes a practical, flexible, and reliable in-memory computing architecture for resistive-memory-based logic designs. Our design uses a new RRAM-based polymorphic in-memory logic gate implementing all 2-input Boolean logic functions to handle real-time applications like search engines. This design reduces the proposed architecture's power-delay product (PDP) compared to competing designs by utilizing the features of the RRAM device and the proposed reconfigurable sensing amplifier. Additionally, the simulation results on the ISCAS-89 and ITC-99 benchmarks at the 7nm technology node show that the suggested architecture's PDP is lower than the comparable state-of-the-art designs. A novel sense amplifier supporting all Boolean logic functions is also proposed to handle the applications with resistive-resistive-based inputs, such as search applications. After retrieving data from the main memory, the suggested sense amplifier computes the desired output. To assess the functionality of the suggested design in the presence of process variations, Monte Carlo simulations are conducted to authenticate the robustness and high-performance operation of the proposed design in different classes of resistive-memory-based logic in the presence of process variations. Our results further demonstrate that, compared to its counterpart, the suggested strategy dramatically reduces the energy consumption of the median, Max, and Min filters in real-world applications.

A high‐capacity and nonvolatile spintronic associative memory hardware accelerator

AbstractSignificant progress has been made in manufacturing emerging technologies in recent years. This progress implemented in‐memory‐computing and neural networks, one of today's hottest research topics. Over time, the need to process complex tasks has increased. This need causes the emergence of intelligent processors. A nonvolatile associative memory based on spintronic synapses utilising magnetic tunnel junction (MTJ) and carbon nanotube field‐effect transistors (CNTFET)‐based neurons is proposed. The proposed design uses the MTJ device because of its fascinating features, such as reliable reconfiguration and nonvolatility. At the same time, CNTFET has overcome conventional complementary metal‐oxide‐semiconductor shortcomings like the short channel effect, drain‐induced barrier lowering, and poor hole mobility. The proposed design is simulated in the presence of process variations. The proposed design aims to increase the number of weights generated in the synapse for higher memory capacity and accuracy. The effect of different tunnel magnetoresistance (TMR) values (100%, 200%, and 300%) on the performance and accuracy of the proposed design has also been investigated. This investigation shows that the proposed design performs well even with a low TMR value, which is very important and remarkable from the fabrication point of view.

Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern

Advances in integrated circuit process technology have led to new defect mechanisms, and weak resistive defects in standard cells have received attention in addition to traditional defect types. Such defects are categorized as small delay defects that affect the reliability of a circuit. The delay introduced by such defects overlaps with the delay distribution resulting from the random process variation. Combining the results of the theoretical analysis, we propose a test method to improve the probability of detecting cell internal weak defects in the presence of process variation. The path with the minimum logic depth is selected as the test path, and the test pattern that enhanced the small delay of weak defects is paired with the test path. The improvements in defect detection probability over traditional tests are demonstrated on the ISCAS89 benchmark circuits. The results show that the proposed method provides an order of magnitude improvement in the probability of detecting cell internal weak defects.

Hybrid MTJ/CNTFET-Based Binary Synapse and Neuron for Process-in-Memory Architecture

This paper proposes a reliable integrated binary synapse and neurons for hardware implementation of binary neural networks. Thanks to the nonvolatile nature of the magnetic tunnel junction ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MTJ</b> ) and the unique features of the carbon nanotube field-effect transistor ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CNTFET</b> ), the proposed design in this paper does not require external memory to store weights and also consumes low static power. Also, due to the proposed circuit structure that did not use sequential parts, the proposed circuit is immune to soft error. Because in binary neural networks, weights are limited to two values of ‘-1’ and ‘1’, the occurrence of soft errors dramatically reduces the accuracy of the network. Simulation results indicate that the proposed design in this paper consumes at least 9% lower power, occupies 34% lower area, and offers a 49% lower power delay area product ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PDAP</b> ). Also, Monte-Carlo simulations have been performed to study the effect of the process variation on the network. The result of the Monte-Carlo simulations shows that the proposed neuron has no logical error in 10000 simulations. Consequently, the accuracy of the network utilizing by the proposed neuron is equal to the software-implemented network and does not decrease even in the presence of process variations.

LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations

This paper proposes a low-cost yet high-coverage design-for-testability (DFT) scheme for improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on introducing a voltage mismatch in the sense amplifier (SA). This mismatch along with the defects in the cell may bias the SA, leading to an incorrect read output which in turn make the HtD faults detectable. The efficacy of the proposed scheme is evaluated by calculating its detection capability in the presence of resistive defects. Evaluation results obtained for a 20nm STT-MRAM memory design show that the proposed scheme provides HtD fault coverage of 81.8% and 86.5%, on average, for intra-cell and inter-cell defects, respectively, with a negligible area overhead (1.1% for a 2Kbit array). In comparison with conventional March tests, which only detect easy-to-detect (EtD) faults, the proposed DFT technique covers both HtD and EtD faults with a faster approach, namely by using a single read operation. Furthermore, to guarantee that the cells affected by HtD faults trigger an incorrect read output under process variation (PV), a timing strategy based on modifying the control unit of the proposed DFT is suggested. The strategy controls the stress introduced by the DFT unit by altering the timing of DFT control signals. The timing alteration enables the detection of HtD faults in the devices with higher deviations from the nominal one due to PV, avoiding yield loss or test escapes.

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1(\mu + 3\sigma)$ </tex-math></inline-formula> of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry.

Understanding interactions between mixture components and process variables

The study of mixture component effects in the presence of process variables has been of interest since the work of Scheffé. A key advantage of designed experiments in general is the ability to estimate and interpret interactions. A unique feature of mixture-process experiments is the potential presence of interactions between the mixture components and the process variables. The classic approach to interpret these has been to use contour plots and evaluate individual interaction coefficients in Scheffé mixture-process models. It is proposed to study the interactions along the Cox component axes, which greatly enhances the insight into the nature of these interactions that can be obtained from contour plots. Further, we propose an alternative analysis that produces estimates of the process variable main effects in mixture-process models. Both graphical and analytical methods are presented. This approach provides an overall view of the main effects and interactions that is consistent with how these terms are evaluated in factorial and response surface experiments with only process variables. Limitations of the classic approach are identified and discussed. Three examples are included to illustrate the approach.

PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory

Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturb, and lower access latency. Despite these advantages, 3D flash memory brings a number of new challenges. First, in 3D flash memory, NAND strings punch through multiple stacked layers to form the 3D infrastructure. Current etching process is unable to manufacture perfect channels with identical feature size. Second, with more stacked layers, the cell current in 3D flash memory is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D flash memory. This article present <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PVSensing</i> , a process-variation-aware space allocation strategy for open-channel SSD with 3D charge-trap flash memory. PVSensing is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PVSensing utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. Three reliability enhancement strategies (i.e., the adaptive creation of fault cubes, the physical block mining, and the live migration of write requests) are proposed. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PVSensing can effectively reduce uncorrectable bit errors, and improve the reliability of critical data with negligible extra erase operations in comparison with representative schemes.

Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning

Design-space exploration for low-power manycore design is a daunting and time-consuming task which requires some complex tools and frameworks to achieve. In the presence of process variation, the problem becomes even more challenging, especially the time associated with trial-and-error selection of the proper options in the tools to obtain the optimal power dissipation. The key contribution of this work is the novel use of machine learning to speed up the design process by embedding the tool expertise needed for low power design-space exploration for manycores into a trained neural network. To enable this, we first generate a large volume of data for 36000 benchmark applications by running them under all possible configurations to find the optimal one in terms of power. This is done using our own tool called LVSiM, a holistic manycore optimization program including process variations. A neural network is trained with this information to build in the expertise. A second contribution of this work is to define a new set of features, relevant to power and performance optimization, when training the neural network. At design time, the trained neural network is used to select the proper options on behalf of the user based on the features of any new application. However, one problem encountered with this approach is that the database constructed for machine learning has many outliers due to randomness associated with process variation which creates a major headache for classification - the supervised learning task performed by neural networks. The third key contribution of this work is a novel data coercion algorithm used as a corrective measure to handle the outliers. The proposed data coercion scheme produces results that are within 3.9&#x0025; of the optimal power consumption compared to 7&#x0025; without data coercion. Furthermore, the proposed method is about an order of magnitude faster than a heuristic approach and two orders of magnitude faster than a brute-force approach for design-space exploration.

Logic Locking Using Emerging 2T/3T Magnetic Tunnel Junctions for Hardware Security

With the advancement of beyond CMOS devices, a new approach to utilize the inherent physics of such emerging structures for various applications is of great interest in recent research. Spintronics-based devices offer key advantages like ease of fabrication with Si-substrate, non-volatile memory, low operational voltage, and non-linear device characteristics, which have shown potential for several emerging fields of study. Hardware security is one of the key interest areas which heavily relies on CMOS-based ICs, and the defense and attack mechanism is mostly based on CMOS-based structures. This work explores several emerging structures based on 2T/3T magnetic tunnel junctions (MTJ) for possible logic locking applications in hardware security systems. We demonstrate the effect of MTJ-based devices to implement logic locking even in the presence of process variations, and its ability of robustness to device imperfections has been evaluated using monte carlo simulations for practical applications.

Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations. Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat. Thus, a special protection mechanism called Balanced Static Power Logic (BSPL) has been proposed very recently. Essentially, fundamental standard cells are re-designed to balance their drain-source leakage current independent of the given input. In this work, we analyze the BSPL concept in more detail and reveal several design issues that limit its effectiveness as a universal logic library. Although balancing drain-source currents remains a valid approach even in more advanced technology generations, we show that it is conceptually insufficient to achieve a fully data-independent leakage behavior in smaller geometries. Instead, we suggest an alternative approach, so-called improved BSPL (iBSPL). To evaluate the proposed method, we use information theoretic analysis. As an attack strategy, we have chosen Moments-Correlating DPA (MCDPA), since this analysis technique does not depend on a particular leakage model and allows a fair comparison. Through these evaluation methods, we show iBSPL demands fewer resources and delivers better balance in the ideal case as well as in the presence of process variations.

Optimization of Split-Plot Design in the Context of Mixture Process Variable Settings

In the presence of process variables, a mixture design has become well-known in statistical modeling due to its utility in modeling the blending surface, which empirically predicts any mixture's response and serves as the foundation for optimizing the expected response blends of different components. In the most common practical situation involving a mixture-process variable, restricted randomization occurs frequently. This problem is solved when the split-plot layout arrangement is used within the constraints. This study's primary goal was to find the best split-plot design (SPD) for the settings mixture-process variables. The SPD was made up of a simplex centroid design (SCD) of four mixture blends and a factorial design with a central composite design (CCD) of the process variable and compared six different context split-plot structure arrangement. We used JMP software version 15 to create D-optimal split-plot designs. The study compared the constructed designs' relative efficiency using A-, D-, I-, and G- optimality criteria. Furthermore, a graphical technique (fraction of design space plot) was used to display, explain, and evaluate experimental designs' performance in terms of precision of the six designs' variance prediction properties. We discovered that arranging subplots with more SCD points than pure mixture design points within SPD with two high process variables is more helpful and provides more precise parameter estimates. We recommend using SPDs in experiments involving mixture process settings developments to measure the mixture components' interaction effects and the processing conditions. Also, the investigation should be set up at each of the points of a factorial design.

SIMULATION OF CONTROL SYSTEM OF THE CHEMICAL-TECHNOLOGICAL PROCESSES

In this work is consider study and analysis of dynamic system for simulation of the technological process under uncertainty and complexity. To study and simulate a complicated technology process we carry out for consideration the technology of the process of roasting in fluidized bed furnaces of polymetallic sulphide ores. The choice is justified by the fact that, operation line producing of polymetallic sulphide ores represents a complex process, is characterized by a big number of transient processes, presence of process variables and deviations from technical regimes. To study process characteristics of any system functioning by means of mathematical methods the process should be formalized. This means, that adequate mathematical model needs to be developed. The choice of mathematical model depends a lot upon the features of the object and its controllability as well as of technological scheme and complexity of processes. Chemical engineering processes are complicated physical and chemical systems. Substance flows, which are part of these systems, are, as a rule, multicomponent. Therefore, for the purpose of study and qualitative control over chemical-engineering processes it is essential to apply the method of mathematic simulation, based on system analysis strategy, analysis of its structure, mathematical formulation development and evaluation of unknown parameters. Controllability means that such system attribute as having control actions, which make it possible to transfer the system from a pre-set initial state to the required condition during finite quantum of time. Therefore, the developed mathematical model of the process or control object should be controllable and stability.

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation- and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dual-threshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs

Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates can diminish these advantages in practice. In this brief, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units.

MATHEMATICAL SIMULATION AND STUDY OF CONTROL STABILITY OF THE CHEMICAL-ENGINEERING PROCESSES IN INDUSTRY

In this work is consider study and analysis of dynamic system for simulation of the technological process under uncertainty and complexity. To study and simulate a complicated technology process we carry out for consideration the technology of the process of roasting in fluidized bed furnaces of polymetallic sulphide ores. The choice is justified by the fact that, operation line producing of polymetallic sulphide ores represents a complex process, is characterized by a big number of transient processes, presence of process variables and deviations from technical regimes. To study process characteristics of any system functioning by means of mathematical methods the process should be formalized. This means, that adequate mathematical model needs to be developed. The choice of mathematical model depends a lot upon the features of the object and its controllability as well as of technological scheme and complexity of processes. Chemical engineering processes are complicated physical and chemical systems. Substance flows, which are part of these systems, are, as a rule, multicomponent. Therefore, for the purpose of study and qualitative control over chemical-engineering processes it is essential to apply the method of mathematic simulation, based on system analysis strategy, analysis of its structure, mathematical formulation development and evaluation of unknown parameters. Controllability means that such system attribute as having control actions, which make it possible to transfer the system from a pre-set initial state to the required condition during finite quantum of time. Therefore, the developed mathematical model of the process or control object should be controllable and stability.

New Approach for Designing and Optimally Selecting the Parameters of Graphene nano-ribbon Transistors in the Presence of Process Variation

GNRFET Graphene Nano-Ribbon Field-Effect Transistor is sensitive to geometric parameters. Therefore, changing parameters circuit characteristics can be improved or degraded. In this study, we propose a new approach to optimizing the GNRFETs. The effect of geometric and process parameters such as chirality, channel length, width, line edge roughness, oxide thickness, and doping on characteristics of an inverter gate is investigated based on GNRFET. Analysis of power consumption, delay, PDP, and SNM results indicate that GNRFETs adjustable parameters can significantly affect circuit performance. It is shown that SNM increases by changing channel length and width. Moreover, by reducing the channel length from 20 nm to 10 nm, delay for chirality (6,0) decreases by 50%, and delay for chirality (10,0) decreases by 53%. By increasing the Line Edge Roughness by 20%, power consumption for chirality (10,0) and chirality (6,0) increases by 18% and exponentially, respectively. Also, by decreasing the oxide thickness, SNM and power consumption are increased; however, the delay behaves differently with chiralities (6,0) and (10,0). This research demonstrates the importance of accurately determining the GNRFET adjustable parameters according to the design aims. A set of recommendations is provided for optimal parameters needed by digital circuit designers to use GNRFET in their design optimally.

Design of an Energy-Efficient Radiation-Hardened Non-Volatile Magnetic Latch

By scaling down the technology node to the deep nanoscale, the vulnerability of digital circuits to radiation and the intensive increase of leakage power have become of concern. Accordingly, designing radiation-hardened (rad-hard) memory elements based on non-volatile devices such as magnetic tunnel junction (MTJ) is a promising approach to address these issues. This study proposes a novel robust and energy-efficient rad-hard latch based on a new C-element-based keeper. Moreover, the proposed rad-hard latch is employed to design a highly reliable non-volatile magnetic latch using MTJs. The proposed latches can also be exploited to form a rad-hard magnetic master–slave flip-flop. Simulations based on the 14 nm FinFET and the spin Hall effect (SHE)-assisted perpendicular MTJ models suggest that the proposed designs offer advantageous figures of merit over the prior works. Specifically, the proposed circuits offer up to 52% and 82% improvements in power and delay, respectively, when compared to their state-of-the-art counterparts. Moreover, Monte Carlo simulations validate the robust operation of the proposed design in the presence of process variations.

Ultra-High-Performance Magnetic Nonvolatile Level Converter Flip-Flop with Spin-Hall Assistance for Dual-Supply Systems with Power Gating Architecture

Recently, nonvolatile spintronic memory elements have drawn a lot of attention for designing nanoscale integrated circuit design due to their several advantages such as near-zero static power, high endurance, good scalability, and compatibility with the current process technologies. In this paper, a high-speed and low-power spintronic-based nonvolatile level converter flip-flop (NVLCFF) is proposed. This efficient design facilitates the use of power gating and dual-supply techniques simultaneously for ultra-energy-efficient integrated circuits. The proposed NVLCFF uses the spin Hall effect-assisted spin-transfer torque magnetic tunnel junction (SHE-assisted STT-MTJ) to provide nonvolatile data storage. Furthermore, a new voltage level converter is presented to perform voltage level conversion in the proposed NVLCFF. Elimination of the contention condition, using one reconfigurable MTJ, and no static voltage division in the proposed design lead to considerably higher speed and lower power. The 7-nm FinFET, as one of the leading industrial technologies, is utilized to design the peripheral circuity. The HSPICE simulation results show on average, 64%, 62%, and 35% improvements regarding the power dissipation, backup energy, and restore energy as compared to the other NVLCFFs. Furthermore, comprehensive Monte Carlo simulations demonstrate the robustness of the proposed design in the presence of process variations.

A Novel Oscillation-Based Reconfigurable In-Memory Computing Scheme With Error Correction

In-memory computing promises to overcome memory and power walls by allowing efficient computing of operations inside the memory without the need to explicitly transfer operands back and forth to the processor core. This paradigm is enabled by emerging resistive memory technology and the adjustment of the memory periphery to perform the computation. The existing methods to perform in-memory calculations are either bound to a specific technology or do not scale well for complex multi-input functions. In this article, we propose a new technique for in-memory computing using resistive devices to calculate the symmetric Boolean logic operations for any number of inputs. In our proposed method, we first convert the equivalent resistance state that is generated by storing devices to an electrical oscillation, and later, time-based sensing for these oscillations is employed to generate the required output. Since the computation using our proposed technique is based on the oscillations, it can be easily tuned for different computation tasks depending on applications. This is used to implement an efficient column-wise error-correction code (ECC) for in-memory computing. We have performed extensive Monte Carlo simulations to confirm the functionality of our proposed method in the presence of process variation. Compared with state-of-the-art comparative-based schemes, for a two-bit in-memory XOR computation, our proposed technique can improve dynamic energy by 41% and additionally scales well for more number of inputs. Results show a reduction of the parity overhead by 10% in our evaluated memory and an area reduction of 21% compared with conventional ECC circuits.