Bits Of Precision Research Articles

Spatial sigma-delta modulation for coarsely quantized linear, circular, and spherical arrays

Quantization noise shaping, also known as sigma-delta modulation, is widely used in analog-to-digital converters. Such converters oversample a signal in time, quantize it to one or a few bits of precision, and then use analog feedback to shape quantization noise outside the band of interest, producing a high-precision output. Similarly, if a sensor array is spatially oversampled so that its elements are much less than one-half wavelength apart, then quantization noise can be propagated between channels to shape its spatial distribution. A beamformer acts as a spatial filter, removing shaped quantization noise to produce a high-precision output even with coarsely quantized sensors. Spatial sigma-delta modulation has been explored primarily for radio-frequency applications using linear arrays. In this presentation, we apply spatial noise shaping to dense acoustic sensor arrays, including circular and spherical arrays. For immersive audio applications, we demonstrate how noise-shaping feedback can be used to push quantization noise into higher-order Ambisonic modes.

Dynamic Precision Analog Computing for Neural Networks

Analog electronic and optical computing exhibit tremendous advantages over digital computing for accelerating deep learning when operations are executed at low precision. Although digital architectures support programmable precision to increase efficiency, analog computing architectures today only support a single, static precision. In this work, we characterize the relationship between the effective number of bits (ENOB) of precision of analog processors, which is limited by noise, and digital bit precision for quantized neural networks. We propose extending analog computing architectures to support dynamic levels of precision by repeating operations and averaging the result, decreasing the impact of noise. To utilize dynamic precision, we propose a method for learning the precision of each layer of a pre-trained model without retraining network weights. We evaluate this method on analog architectures subject to shot noise, thermal noise, and weight noise and find that employing dynamic precision reduces energy consumption by up to 89% for computer vision models such as Resnet50 and by 24% for natural language processing models such as BERT. In one example, we apply dynamic precision to a shot-noise limited homodyne optical neural network and simulate inference at an optical energy consumption of 2.7 aJ/MAC for Resnet50 and 1.6 aJ/MAC for BERT with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${&lt; }2\%$</tex-math></inline-formula> accuracy degradation, implying that the optical energy consumption is unlikely to be the dominant cost.

An 8-bit integer true periodic orbit PRNG based on delayed Arnold’s cat map

Designing a pseudo-random number generator (PRNG) exhibiting true periodic orbits with large periods is promising for embedded applications. Implementing chaotic behaviors on a finite precision digital platform using conventional unsigned integer or floating-point arithmetic yields short period limit-cycles. It leads the output to diverge from the true chaotic orbits. This paper presents an unsigned integer encoded PRNG based on the delayed quantized Arnold’s Cat Map (QACM) that exhibits true periodic orbits with large periods. The proposed PRNG is obtained by delaying one of the 2-D QACM outputs with a linear feedback shift register (LFSR) thereby increasing its period. By investigating its period, we show that the periodicity increases with an increase in the delay and bit-precision. We also present the proposed PRNG unit’s hardware architecture and its synthesis results targeting on a Xilinx Zynq 7000 Field Programmable Gate Array (FPGA) with 8-bit precision and delay δ=58. Further, we synthesize the design using 90 nm CMOS technology for ASIC realization. The synthesis results demonstrate the throughput as 2.208 Gbps and 5.46 Gbps at 138 MHz and 342 MHz operating frequency on FPGA and ASIC respectively. We experimentally evaluate the performance of random numbers using the NIST 800-22-1 tests along with the correlation and key sensitivity tests.

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

This paper proposes a tiny and error-tolerant convolutional long short-term memory network (ConvLSTM) for event-based vision sensor data processing with computation-in-memory (CiM) that utilizes resistive random-access memory (ReRAM). To handle the event data by ConvLSTM, the type and parameter of event representation are optimized to pre-process event data. To realize tiny and error-tolerant ConvLSTM CiM, reductions of the bit precision and error tolerance in each ConvLSTM layer and weight are considered. On the other hand, reducing the bit precision degrades inference accuracy and error tolerance. ReRAM has non-idealities such as conductance variation and wearing out by Set/Reset cycles that induces bit inversion. Thus, the bit error rate at each Set/Reset cycle is investigated, and the bit precision of the weight is optimized to accept a bit error rate of 0.1% in simulation. The proposed tiny ConvLSTM can reduce the size of memory by 91% compared with non-optimized ConvLSTM for which weight is represented in 32-bit precision.

Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications

State-of-the-art compact models such as MobileNets and EfficientNets are structured using a linear bottleneck and inverted residuals. Hardware architecture using a single dataflow strategy fails to balance the required memory bandwidth with the given computational resources. This work presents a heterogeneous dual-core accelerator that performs a block-wise pipelined process as a unit using a bottleneck-stationary (BS) dataflow. The BS greatly relieves the requirement on DRAM bandwidth and on-chip SRAM capacity. A look-behind-only attention is also proposed as a co-optimized algorithm. Compared to the state-of-the-art hardware scheme, the proposed accelerator demonstrates a reduction of 1.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.9\times $ </tex-math></inline-formula> in latency and 2.2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> in energy consumption, respectively.For verification, the accelerator with a 16-bit integer precision was implemented using 28nm CMOS process. Measurements show energy efficiencies of 0.5-to-3.75 TOPS/W in a supply voltage range of 0.55-to-1.15V.

An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning

This article presents an enhanced-performance, hardware-efficient Softmax Function (SF) for a deep neural network accelerator. Softmax is used in the classification layer in deep learning models and is also used in hidden layers of advanced neural networks like Transformer and Capsule networks. The major challenge in designing efficient hardware architecture of SF is complex exponential and division computational sub-blocks. Utilizing mutual exclusivity of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CO-ordinate Rotational DIgital Computer</i> (CORDIC) algorithm, hardware-optimized pipelined CORDIC-based architecture is considered for the area, power, and enhanced throughput design. In order to maintain good accuracy in the deep learning models, the proposed SF design undergoes a Pareto study on the variation of accuracy for the number of pipeline stages. The proposed design is quantized to 16-bit precision, and inference accuracy is validated for various datasets. The SF is prototyped using Xilinx Zynq FPGA and can be operated at 685MHz. Also, ASIC implementation is performed for 45nm technology node at 5GHz of maximum operating frequency. The design achieves a validation accuracy loss of less than 2% in the account of reduced silicon area and Energy-Delay-Product(EDP) (by 12×). Post synthesis simulation result illustrates that the proposed design achieves 3× better performance in terms of area, power, and logic delay compared to state-of-the-art architectures.

Certified Newton schemes for the evaluation of low-genus theta functions

Theta functions and theta constants in low genus, especially genus 1 and 2, can be evaluated at any given point in quasi-linear time in the required precision using Newton schemes based on Borchardt sequences. Our goal in this paper is to provide the necessary tools to implement these algorithms in a provably correct way. In particular, we obtain uniform and explicit convergence results in the case of theta constants in genus 1 and 2, and theta functions in genus 1: the associated Newton schemes will converge starting from approximations to N bits of precision for N = 60, 300, and 1600 respectively, for all suitably reduced arguments. We also describe a uniform quasi-linear time algorithm to evaluate genus 2 theta constants on the Siegel fundamental domain. Our main tool is a detailed study of Borchardt means as multivariate analytic functions.

VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators

Non-volatile memory (NVM) such as RRAM and PCM has become the key component in high energy efficiency computing-in-memory (CIM) architectures. However, the computing accuracy and energy efficiency improvement of conventional 1T1R RRAM array based current sensing CIM scheme is hindered by device variation and large output current. In this work, we propose a voltage sensing differential column architecture (VSDCA) based on 1T2R RRAM array for binary memory and CIM applications. The memory mode of VSDCA macro can improve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.12\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.29\times $ </tex-math></inline-formula> relative read margin compared to conventional 1T1R current sensing memory. The computing mode supports 8-bit input, 9-bit weight and 18-bit output high precision and rows fully parallel computing. The VSDCA macro design is evaluated under SMIC 40 nm technology node, the energy efficiency for the high precision CIM reaches 39.52 TOPS/W. The CIFAR10 inference accuracy of the simulated VGG16 and ResNet18 model is 85.91% and 89.32% respectively.

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. We present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

TinyML Model for Classifying Hazardous Volatile Organic Compounds Using Low-Power Embedded Edge Sensors: Perfecting Factory 5.0 Using Edge AI

In this letter, we present an intelligent chemical sniffer, capable of detecting hazardous volatile organic compounds (VOCs) using artificial intelligence deployed at the edge. The proposed solution utilizes a multichannel metal–oxide–semiconductor gas sensor for generating unique signature responses from the organic compounds. These signature responses are then used for training a quantized neural network model in the cloud and then deployed onto an embedded development platform for edge inference. In this approach, we utilized TensorFlow Lite for microcontrollers, an edge computing framework (developed by Google) to quantize a 32-bit floating point precision neural network model into an 8-bit integer precision model for deployment on low-power and low-memory footprint embedded edge devices. Our quantized model was able to successfully classify all the six VOCs (i.e., Xylene, Hexane, Acetone, Toluene, Methanol, and Butanol) with accuracies of 99.8 and 100% on the validation and test datasets, respectively. More than 50% reduction in on-device RAM and Flash memory usage were measured for the 8-bit quantized model when compared with the equivalently performing 32-bit floating point model for relatively same inference speed on the edge sensing device. The proposed solution paves the way for the mass-scale deployment of such intelligent chemical sensing solutions in the next-generation automated smart factories.

Real-Time LiDAR Point Cloud Compression Using Bi-Directional Prediction and Range-Adaptive Floating-Point Coding

Due to the large amount of data involved in the three-dimensional (3D) LiDAR point clouds, point cloud compression (PCC) becomes indispensable to many real-time applications. In autonomous driving of connected vehicles for example, point clouds are constantly acquired along the time and subjected to be compressed. Among the existing PCC methods, very few of them have effectively removed the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">temporal</i> redundancy inherited in the point clouds. To address this issue, a novel lossy LiDAR PCC system is proposed in this paper, which consists of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inter</i> -frame coding and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">intra</i> -frame coding. For the former, a deep-learning approach is proposed to conduct bi-directional frame prediction using an asymmetric residual module and 3D space-time convolutions; the proposed network is called the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bi-directional prediction network</i> (BPNet). For the latter, a novel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">range-adaptive floating-point coding</i> (RAFC) algorithm is proposed for encoding the reference frames and the B-frame prediction residuals in the 32-bit floating-point precision. Since the pixel-value distribution of these two types of data are quite different, various encoding modes are designed for providing adaptive selection. Extensive simulation experiments have been conducted using multiple point cloud datasets, and the results clearly show that our proposed PCC system consistently outperforms the state-of-the-art MPEG G-PCC in terms of data fidelity and localization, while delivering real-time performance.

Nanosecond machine learning regression with deep boosted decision trees in FPGA for high energy physics

We present a novel application of the machine learning / artificial intelligence method called boosted decision trees to estimate physical quantities on field programmable gate arrays (FPGA). The software package fwXmachina features a new architecture called parallel decision paths that allows for deep decision trees with arbitrary number of input variables. It also features a new optimization scheme to use different numbers of bits for each input variable, which produces optimal physics results and ultraefficient FPGA resource utilization. Problems in high energy physics of proton collisions at the Large Hadron Collider (LHC) are considered. Estimation of missing transverse momentum (ET miss) at the first level trigger system at the High Luminosity LHC (HL-LHC) experiments, with a simplified detector modeled by Delphes, is used to benchmark and characterize the firmware performance. The firmware implementation with a maximum depth of up to 10 using eight input variables of 16-bit precision gives a latency value of \U0001d4aa(10) ns, independent of the clock speed, and \U0001d4aa(0.1)% of the available FPGA resources without using digital signal processors.

Roulette: A Diverse Family of Feasible Fault Attacks on Masked Kyber

At Indocrypt 2021, Hermelink, Pessl, and Pöppelmann presented a fault attack against Kyber in which a system of linear inequalities over the private key is generated and solved. The attack requires a laser and is, understandably, demonstrated with simulations—not actual equipment. We facilitate and diversify the attack in four ways, thereby admitting cheaper and more forgiving fault-injection setups. Firstly, the attack surface is enlarged: originally, the two input operands of the ciphertext comparison are covered, and we additionally cover re-encryption modules such as binomial sampling and butterflies in the last layer of the inverse numbertheoretic transform (INTT). This extra surface also allows an attacker to bypass the custom countermeasure that was proposed in the Indocrypt paper. Secondly, the fault model is relaxed: originally, precise bit flips are required, and we additionally support set-to-0 faults, random faults, arbitrary bit flips, and instruction skips. Thirdly, masking and blinding methods that randomize intermediate variables kindly help our attack, whereas the IndoCrypt attack is like most other fault attacks either hindered or unaltered by countermeasures against passive side-channel analysis (SCA). Randomization helps because we randomly fault intermediate prime-field elements until a desired set of values is hit. If these prime-field elements are represented on a circle, which is a common visualization, our attack is analogous to spinning a roulette wheel until the ball lands in a desired set of pockets. Hence, the nickname. Fourthly, we accelerate and improve the error tolerance of solving the system of linear inequalities: run times of roughly 100 minutes are reduced to roughly one minute, and inequality error rates of roughly 1% are relaxed to roughly 25%. Benefiting from the four advances above, we use a reasonably priced ChipWhisperer® board to break a masked implementation of Kyber running on an ARM Cortex-M4 through clock glitching.

Deterministic Linear Time for Maximal Poisson‐Disk Sampling using Chocks without Rejection or Approximation

AbstractWe show how to sample uniformly within the three‐sided region bounded by a circle, a radial ray, and a tangent, called a “chock.” By dividing a 2D planar rectangle into a background grid, and subtracting Poisson disks from grid squares, we are able to represent the available region for samples exactly using triangles and chocks. Uniform random samples are generated from chock areas precisely without rejection sampling. This provides the first implemented algorithm for precise maximal Poisson‐disk sampling in deterministic linear time. We prove O(n · M(b) log b), where n is the number of samples, b is the bits of numerical precision and M is the cost of multiplication. Prior methods have higher time complexity, take expected time, are non‐maximal, and/or are not Poisson‐disk distributions in the most precise mathematical sense. We fill this theoretical lacuna.

Precision requirements and data compression in CryoEM/CryoET

With larger, higher speed detectors and improved automation, individual CryoEM instruments are capable of producing a prodigious amount of data each day, which must then be stored, processed and archived. While it has become routine to use lossless compression on raw counting-mode movies, the averages which result after correcting these movies no longer compress well. These averages could be considered sufficient for long term archival, yet they are conventionally stored with 32 bits of precision, despite high noise levels. Derived images are similarly stored with excess precision, providing an opportunity to decrease project sizes and improve processing speed. We present a simple argument based on propagation of uncertainty for safe bit truncation of flat-fielded images combined with lossless compression. The same method can be used for most derived images throughout the processing pipeline. We test the proposed strategy on two standard, data-limited CryoEM data sets, demonstrating that these limits are safe for real-world use. We find that 5 bits of precision is sufficient for virtually any raw CryoEM data and that 8–12 bits is sufficient for intermediate averages or final 3-D structures. Additionally, we detail and recommend specific rules for discretization of data as well as a practical compressed data representation that is tuned to the specific needs of CryoEM.

WDM equipped universal linear optics for programmable neuromorphic photonic processors

Non-von-Neumann computing architectures and deep learning training models have sparked a new computational era where neurons are forming the main architectural backbone and vector, matrix and tensor multiplications comprise the basic mathematical toolbox. This paradigm shift has triggered a new race among hardware technology candidates; within this frame, the field of neuromorphic photonics promises to convolve the targeted algebraic portfolio along a computational circuitry with unique speed, parallelization, and energy efficiency advantages. Fueled by the inherent energy efficient analog matrix multiply operations of optics, the staggering advances of photonic integration and the enhanced multiplexing degrees offered by light, neuromorphic photonics has stamped the resurgence of optical computing brining a unique perspective in low-energy and ultra-fast linear algebra functions. However, the field of neuromorphic photonics has relied so far on two basic architectural schemes, i.e., coherent linear optical circuits and incoherent WDM approaches, where wavelengths have still not been exploited as a new mathematical dimension. In this paper, we present a radically new approach for promoting the synergy of WDM with universal linear optics and demonstrate a new, high-fidelity crossbar-based neuromorphic photonic platform, able to support matmul with multidimensional operands. Going a step further, we introduce the concept of programmable input and weight banks, supporting in situ reconfigurability, forming in this way the first WDM-equipped universal linear optical operator and demonstrating different operational modes like matrix-by-matrix and vector-by-tensor multiplication. The benefits of our platform are highlighted in a fully convolutional neural network layout that is responsible for parity identification in the MNIST handwritten digit dataset, with physical layer simulations revealing an accuracy of ∼94%, degraded by only 2% compared to respective results obtained when executed entirely by software. Finally, our in-depth analysis provides the guidelines for neuromorphic photonic processor performance improvement, revealing along the way that 4 bit quantization is sufficient for inputs, whereas the weights can be implemented with as low as 2 bits of precision, offering substantial benefits in terms of driving circuitry complexity and energy savings.

Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training

As machine learning (ML) and artificial intelligence (AI) have become mainstream technologies, many accelerators have been proposed to cope with their computation kernels. However, they access the external memory frequently due to the large size of deep neural network model, suffering from the von Neumann bottleneck. Moreover, as privacy issue is becoming more critical, on-device training is emerging as its solution. However, on-device training is challenging because it should perform the training under a limited power budget, which requires a lot more computations and memory accesses than the inference. In this paper, we present an energy-efficient processing-in-memory (PIM) architecture supporting end-to-end on-device training named T-PIM. Its macro design includes an 8T-SRAM cell-based PIM block to compute in-memory <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AND</i> operation and three computational datapaths for end-to-end training. Each of three computational paths integrates arithmetic units for forward propagation, backward propagation, and gradient calculation and weight update, respectively, allowing the weight data stored in the memory stationary. T-PIM also supports variable bit precision to cover various ML scenarios. It can use fully variable input bit precision and 2-bit, 4-bit, 8-bit, and 16-bit weight bit precision for the forward propagation and the same input bit precision and 16-bit weight bit precision for the backward propagation. In addition, T-PIM implements sparsity handling schemes that skip the computation for input data and turn off the arithmetic units for weight data to reduce both unnecessary computations and leakage power. Finally, we fabricate the T-PIM chip on a 5.04mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die in a 28-nm CMOS logic process. It operates at 50–280MHz with the supply voltage of 0.75–1.05V, dissipating 5.25–51.23mW power in inference and 6.10–37.75mW in training. As a result, it achieves 17.90–161.08TOPS/W energy efficiency for the inference of 1-bit activation and 2-bit weight data, and 0.84–7.59TOPS/W for the training of 8-bit activation/error and 16-bit weight data. In conclusion, T-PIM is the first PIM chip that supports end-to-end training, demonstrating 2.02 times performance improvement over the latest PIM that partially supports training.

An 8-bit precision cipher for fast image encryption

Implementing chaos based ciphers usually involves 32-bit floating-point arithmetics that is hardware resources costly. The limitation of the computational precision is hardware imposed and transforms chaotic orbits into limit cycles with short periods, hence alters their randomness. In cryptographic applications, short period dynamics and weak randomness result in security issues. In order to address this concern, we propose an 8-bit precision cipher that can be implemented with low-end microprocessors running 8-bit integer arithmetics. The cipher includes a quantized pseudo-random number generator (QPRNG) based on a 16-dimensional quantized Arnold’s cat map (QACM). We used entropy measure, statistical, sensitivity and key space analyses to evaluate its security level under limited computational precision. Simulation results attest that it is as highly secure as those involving real-number arithmetics, even for only 8-bit precision. We also showed that the period of the proposed QACM can be chosen such that Tx > 1027, which is very large as compared to existing QACM. Such a large period implies a high randomness of the derived QPRNG that is confirmed by statistical NIST tests. Contrary to existing ciphers that include other chaotic systems than the QACM for strengthening the security level, ours is exclusively based on the QACM and is fast, despite the included high-dimensional QACM.

Fluid Simulations Accelerated With 16 Bits: Approaching 4x Speedup on A64FX by Squeezing ShallowWaters.jl Into Float16.

Most Earth‐system simulations run on conventional central processing units in 64‐bit double precision floating‐point numbers Float64, although the need for high‐precision calculations in the presence of large uncertainties has been questioned. Fugaku, currently the world's fastest supercomputer, is based on A64FX microprocessors, which also support the 16‐bit low‐precision format Float16. We investigate the Float16 performance on A64FX with ShallowWaters.jl, the first fluid circulation model that runs entirely with 16‐bit arithmetic. The model implements techniques that address precision and dynamic range issues in 16 bits. The precision‐critical time integration is augmented to include compensated summation to minimize rounding errors. Such a compensated time integration is as precise but faster than mixed precision with 16 and 32‐bit floats. As subnormals are inefficiently supported on A64FX the very limited range available in Float16 is 6 × 10−5 to 65,504. We develop the analysis‐number format Sherlogs.jl to log the arithmetic results during the simulation. The equations in ShallowWaters.jl are then systematically rescaled to fit into Float16, using 97% of the available representable numbers. Consequently, we benchmark speedups of up to 3.8x on A64FX with Float16. Adding a compensated time integration, speedups reach up to 3.6x. Although ShallowWaters.jl is simplified compared to large Earth‐system models, it shares essential algorithms and therefore shows that 16‐bit calculations are indeed a competitive way to accelerate Earth‐system simulations on available hardware.

Efficient high-dynamic-range depth map processing with reduced precision neural net accelerator

Depth sensing technology has become important in a number of consumer, robotics, and automated driving applications. However, the depth maps generated by such technologies today still suffer from limited resolution, sparse measurements, and noise, and require significant post-processing. Depth map data often has higher dynamic range than common 8-bit image data and may be represented as 16-bit values. Deep convolutional neural nets can be used to perform denoising, interpolation and completion of depth maps; however, in practical applications there is a need to enable efficient low-power inference with 8-bit precision. In this paper, we explore methods to process high-dynamic-range depth data using neural net inference engines with 8-bit precision. We propose a simple technique that attempts to retain signal-to-noise ratio in the post-processed data as much as possible and can be applied in combination with most convolutional network models. Our initial results using depth data from a consumer camera device show promise, achieving inference results with 8-bit precision that have similar quality to floating-point processing.