Precharge Scheme Research Articles

DC-Bus Voltage Sensorless Control of an Active Rectifier with Modular Multilevel Converter

The modular multilevel converter (MMC) is recognized as one of the promising converters for the electrification of ships and railways. Among different energy conversion stages, the MMC-based rectifier should realize stable DC output voltage and accurate input current control. However, output DC-bus voltage sensors must be installed, which are costly and bulky. This paper presents a simple but effective control method for the MMC-based rectifier, removing the traditional output DC-bus voltage sensor. An accurate evaluation model of DC-bus voltage is developed as well as the implementing method. Meanwhile, a safe and fast pre-charging scheme is presented for the MMC-based rectifier without output voltage sensors. The fault-tolerant capability of the proposed method when the failure of the output DC-bus voltage sensor occurs is examined. Simulated and testing results demonstrate that the proposed method presents not only excellent steady-state and dynamic performance but also strong fault-tolerant capability. The proposed evaluation model for DC-bus voltage has a high accuracy with an error of less than 1%. Besides, the pre-charging time is less than 0.5 s using the proposed sensorless control.

A New Thyristor-Based DC Circuit Breaker Using Diode Clamping Switching

It has been widely accepted to apply dc circuit breakers (DCCBs) to protect dc grids. Nevertheless, existing DCCBs have one or more following limitations: insulation recovery scheme of mechanical switch, additional precharge power supply, high conduction loss, unreliable current-breaking process, and unidirectional design. In this letter, a new DCCB with low conduction loss, simple precharging scheme, and reliable breaking ability is proposed. The proposed DCCB could break both fault and operating current actively with the same simple operation sequences. Moreover, bidirectional topology possessing all advantages mentioned previously is also presented. Topology introduction, parameters designing, and scaled-down experiment of the proposed DCCB are all presented in the letter.

A novel dual-reference sensing scheme for computing in memory within STT-MRAM

With the rapid development of the Internet of Things and artificial intelligence, it is more and more difficult for the existing hardware structure to process billions of data. In conventional Von-Neumann architectures, the well-known “memory wall” becomes a critical barrier to limit bandwidth. In order to solve this problem, computing in memory (CIM) within STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) emerges gradually. However, CIM requires multiple memory units in parallel, resulting in higher reading error rate. In this paper, a novel dual-reference sensing scheme (NDRS) is proposed for hybrid CMOS/MTJ logic circuits. By exploiting novel precharge scheme and adding inverter to amplify signals, NDRS scheme can improve CIM reliability significantly. Under the 40 nm technology node and a physics-based MTJ compact model, 1000 times Monte Carlo simulation shows that AND logic operation error rate is ∼7.42% and OR logic operation error rate is ∼2.67%.

A Highly Integrated 3-Phase 4:1 Resonant Switched-Capacitor Converter With Parasitic Loss Reduction and Fast Pre-Charge Startup

This brief proposes a highly-integrated 3-phase ( 3Φ) 4:1 resonant switched-capacitor (ReSC) converter with parasitic capacitor soft charging for Internet-of-Things devices, reducing the current stress at the point of load. Both the 3Φ resonant operation and the parasitic loss reduction schemes improve the power conversion efficiency. Also, this 3Φ-ReSC converter implements a flying capacitor pre-charge scheme to guarantee a safe startup. The chip, fabricated in a 65-nm CMOS process, occupies a silicon area of 1.39 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . We achieve a peak efficiency of 85.5% and a maximum output current of 130mA, in a mm-sized solution, with an input range of 2.3 V - 2.5 V.

Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation

As basic components, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true-single-phase-clocked (TSPC) FF is proposed. With the employment of input-aware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. Postlayout simulations based on SMIC 55-nm CMOS technology show that at a supply voltage of 1.2 V, the power consumption of the proposed FF is 84.37% lower than that of conventional transmission-gate flip-flop (TGFF) at 10% data activity. The reduction rate is increased to 98.53% as the data activity goes down to 0%. When the supply voltage decreases to 0.6 V, the proposed FF consumes only 0.411 fJ/cycle at 10% data activity, which is 84.23% lower than TGFF. Measurement results of ten test chips demonstrate the great energy efficiency of the proposed FF. Furthermore, the CK-to-Q delay of the proposed FF is 26.18% lower than that of TGFF at a supply voltage of 1.2 V.

All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash

A NAND flash memory senses a cell current in the range of tens of nA, which is smaller than other nonvolatile memories in the read operation. Because of the small cell current, it is difficult to improve the latency and accuracy of the read operation. The improvement of read latency has been a major challenge for the all-bit-line (ABL) sensing architecture because the BL coupling capacitance caused by the off cell limits the BL pre-charge time. In this paper, a high-speed BL pre-charge scheme with an off-cell-like BL locking (OCBLL) is proposed to reduce the BL coupling capacitance between the off-cell BL and the adjacent BL. The deviation of the latch trip voltage caused by the variations in process, voltage, and temperature (PVT) presents another challenge because the deviation increases the read error owing to the small cell current. A sense-out-node amplification (SOA) scheme is proposed to amplify the voltage of the sense-out-node according to the cell current. The SOA scheme generates a large voltage difference despite the small cell current difference. In the simulation with HSPICE models under the same BL-to-BL coupling ratio, it is found that the proposed schemes improve the speed of the BL pre-charge operation by 75% and reduce the read error by 57%.

Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding

This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of “0s”. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for “0”. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 μW and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V.

A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the ${V}_{\textsf {pass}}$ window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.

Charge sharing write driver and half‐ pre‐charge 8T SRAM with virtual ground for low‐power write and read operation

A novel write bitline (BL) charge sharing write driver (CSWD) and a half-V DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V DD to V DD essentially reduces the write dynamic power dissipation by 50%. Half-V DD precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I on /I off ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN) of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.

Enhanced line commutated converter with embedded fully controlled sub‐modules to mitigate commutation failures in high voltage direct current systems

An enhanced line commutated converter (E-LCC) with embedded fully controlled sub-modules (SMs) to mitigate commutation failures (CFs) in high voltage direct current (HVDC) system is proposed in this study. The main feature of E-LCC is that each arm is composed of thyristor valves and series connected fully controlled SMs. The operation modes and voltage–current stresses of embedded SMs in E-LCC are studied. Then the control strategy, including the pre-charging scheme of SMs and the coordination control method between the thyristor valves and the SMs, is presented. On the basis of the derived equivalent commutation circuit of E-LCC-based HVDC (E-LCC-HVDC), the dynamic characteristics of the commutation process are investigated. Then, the impact of E-LCC-HVDC on CFs mitigation is theoretically analysed. To validate the proposed E-LCC-HVDC, the simulation study is conducted in the electromagnetic transient simulation program PSCAD/EMTDC. The results show that with the embedded SMs, the proposed E-LCC-HVDC has the ability to mitigate the CFs and alleviate the power interruption during the AC faults effectively. Furthermore, the theoretical analysis and the presented control method for E-LCC-HVDC are also validated.

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

Phase-change random access memory (PRAM) is considered to be one of the most promising storage class memory candidates. In this paper, several circuit techniques are introduced to satisfy the target yield and sensing time requirements of an 8-Gb PRAM. First, we propose a temperature-tracking reference current generator to compensate for the variation in data current caused by the change in the resistance of phase-change materials. Second, an adaptive precharge scheme to solve the problem of large parasitic resistances and capacitances of a global bitline is proposed. Finally, we introduce noise compensation schemes to reduce coupling noise. The verification of the proposed circuit techniques is performed by HSPICE simulation using the 0.25- $\mu{\rm m}$ model parameters used in peripheral circuit of Samsung's 20 nm PRAM technology. The sensing scheme using temperature tracking reference current generator achieves $9.32\sigma$ ( $\sim$ 100%) of read access pass yield in 8-Gb PRAM and 99 ns of the sensing time is achieved using the adaptive precharge scheme and noise compensation schemes.

Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives

In Part II of this paper, the potential of tunnel FETs (TFETs) for ultra-low voltage (ULV)/ultra-low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of appropriate reference circuits. Critical issues arising at ultra-low voltages are analyzed, including static robustness of TFET logic gates, performance degradation, and sensitivity to process variations. Guidelines to design ultra-low energy standard cell libraries are derived. The minimum energy point is analyzed in a wide range of conditions, and guidelines for microarchitectural optimization for ultra-low energy are introduced. Voltage scalability of static RAM memories is also analyzed as main limitation to aggressive voltage scaling of very large scale integration (VLSI) systems, and improved precharge schemes are introduced to reduce leakage. The impact of variations of the main device parameters on VLSI digital circuits is investigated to identify the most critical variations that need to be controlled at process level. This investigation permits to understand the potential of TFETs and their advantages over traditional devices within a unitary framework that is based on fair design and comparison from device to circuit level, as well as to develop clear design perspectives in the context of ULV/ULP VLSI digital circuits.

Low Power Programmable Shift Register With Depletion Mode Oxide TFTs for High Resolution and High Frame Rate AMFPDs

This paper demonstrates a programmable pulse width shift register using depletion mode oxide TFTs for high resolution and high frame rate displays. The proposed shift register is adopted for a pre-charging scheme in a multi-frame-rate display panel because the gate pulse width is programmable only by adjusting the start pulse width without any additional clock signals and reconfiguration of interconnection. To cope with the depletion-mode issue that TFTs are turned on even at zero gate-source voltage, the modified circuits are introduced, compared to the previous LTPS version of a programmable shift register. In addition, the power consumption is reduced significantly by means of a new inverter circuit. The proposed circuit is verified by SPICE for 50 stages and the estimated power consumption is 5.01 mW in the case of two line time pulse width, which is lower than 9.76 mW of a previous oxide TFT overlap shift register by 48.7%.

An Ultra Low-Power Solution for EEPROM in Passive UHF RFID Tag IC With a Novel Read Circuit and a Time-Divided Charge Pump

A dual power supply ultra low-power 1 kbits EEPROM for passive UHF RFID is presented. The read power source is 1 V, while the write power source is 1.65 V, which is only activated in the write mode. To reduce the power of the read circuit without impacting the performance, a pre-charge scheme, a feedback scheme and a self-detect circuit, combined with a special read time sequence are adopted. A time-divided charge pump is proposed to reduce the current surge of the charge pump at the startup phase. The EEPROM IP has been fabricated in a SMIC 0.18 μm 2P4M EEPROM process. The die size of the proposed EEPROM IP is 0.12 mm2. The read and write currents of the EEPROM IP are 1.18 μA and 33 μA respectively. Under a 110 temperature variation, the power variation of the read operation is 15%. The EEPROM IP is then verified in a full UHF RFID chip. Tested by a commercial reader at 4 W EIRP, the maximum read and write communication ranges are 6 m and 3 m respectively. The measured voltage drop of the output of rectifier Vrect caused by the current surge of the charge pump is smaller than 50 mV.

35.4: Programmable Pulse Width LTPS TFT Shift Register for High Resolution and High Frame Rate Active Matrix Flat Panel Displays

AbstractThis paper proposes a programmable pulse width LTPS TFT shift register where an output pulse width is programmed only by adjusting a start pulse width without any additional clock signals and reconfiguration. Since an overlap interval of the output pulses is easily controlled in the shift register which operates with precharging scheme, the proposed shift register can be applied to high resolution and high frame rate display without the problem of insufficient line time. The performance of this circuit is verified by SMART SPICE at low‐temperature poly silicon (LTPS) thin film transistor (TFT) process. The pulse width is changed by the step size of two line time with only two input clock signals which leads to small area for circuit implementation and simulated power consumption is similar to that of the conventional shift register.

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

Input filter pre-charge scheme for high-power PWM-current source rectifiers connected to a weak utility supply

High-power PWM current source rectifiers are normally connected to the ac grid by means of a lightly damped LC input filter. Pre-charge schemes employing pre-insertion resistors are typically used to mitigate the over-voltage across the filter capacitors during the connection to the grid. However, noticeable distortion of the grid voltage may still occur during the insertion of the input filter to the grid. This is particularly true at low ratios of the supply fault level to the converter-rated power and cannot be avoided when conventional pre-charge schemes are used. This study proposes a pre-charge scheme that yields a smooth and controllable connection of the input filter to the grid along with total absence of both over-voltage across the input filter capacitors and voltage distortion on the grid. This is novel and it is of particular interest whenever PWM-CSRs are connected to relatively weak grids. Pre-charge is carried out by the main PWM-CSR converter, which is in turn supplied on its dc-side by a small low-power low-voltage pre-charge converter. This completely eliminates the need for any pre-charge components on the ac-side [which can be bulky and expensive at medium voltage (MV) levels]. Experimental results obtained from a 150 kW PWM-CSR are included in the study.

Fast CR-SRAM Using New Charge-Recycling Scheme

In this paper, a CR-SRAM using new charge recycling scheme is described, novel bit-line pre-charge voltage distribution is proposed. The SRAM pre-charge voltage level is designed by logarithm instead of linear. The new design leads to improvement in speed compared to the original CR-SRAM. Simulation results show that the new CR-SRAM using novel pre-charge voltage distribution scheme reduced the write access time by 34% with 9% power dissipation penalty.

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero margin by more than 500ps. The array voltage window is improved by the programmable BL voltage generator, allowing the embedded DRAM to operate reliably without constraining of the microprocessor voltage supply windows. The 2.5nm gate oxide transistor cell with deep-trench capacitor is accessed by the 1.7 V wordline high voltage (VPP) with V WL low voltage (VWL), and both are generated internally within the microprocessor. This results in a 32 MB on-chip L3 on-chip-cache for 8 cores in a 567 mm POWER7™ die.