Precharge Logic Research Articles

Side-channel attack–resistant PRESENT cipher by versatile key scheduling and compact S-box utilizing optimized three-phase logic design

The most widely used technology at the moment is the Internet of Things (IoT), which is expanding at a rapid pace because it allows us to remotely control and manage a variety of smart devices and relieves us from our demanding daily routines. Technology is also vulnerable to security breaches, as evidenced by the rise in cybercrimes and identity theft. More so than any other known IoT security breach, side-channel analysis is extremely insecure. A current issue for lightweight IoT applications is differential power analysis, a kind of side-channel analysis that is very accurate in obtaining the secret key. As a result, developing a safe style takes more time and effort. PRESENT is an easy-to-use, low-power encryption algorithm that is based on Advanced Encryption Standard (AES) and is utilized in IoT devices like RFID tags and access cards. Even with the plethora of countermeasures proposed in the last ten years, none are able to keep up with the IoT’s rapid expansion. A clever combination of masking and hiding techniques could stop several security breaches. Masked three-phase dual rail pre-charge logic is a new hybrid countermeasure that thwarts combined side-channel attacks and is suggested as a means of attaining the necessary degree of security. The hybrid design utilized in PRESENT resulted in an increase in complexity and required more work in terms of area and power. Consequently, more PRESENT optimization techniques are applied. Additionally, for PRESENT hardware implementation, a flexible key scheduling structure with parallel input and output is proposed. Using the Cadence Virtuoso simulation tool with 180-nm technology, a secured structure combining optimized algorithm and secured logic is designed, and the outcomes are analyzed. Normalized energy deviation (NED)/normalized standard deviation (NSD) analysis and Pearson correlation are used to analyze safety. The simulation results for the gates show that our proposed logic has the lowest values of NED and NSD at the assigned frequencies. When compared with side-channel analysis, the outcomes have shown to be both safe and effective. In comparison to earlier designs, the suggested system’s area and power consumption are cut by 67% and 64%, respectively.

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.

Secure Path Balanced BDD-Based Pre-Charge Logic for Masking

This work presents a novel path balanced masked dual-rail pre-charge circuit design scheme based on binary decision diagrams (BDD), using one mask bit per output. It has been applied for achieving masked implementations of two common lightweight ciphers, namely Present and Lucifer. BDD based logic design is achieved using the CUDD tool and applying suitable variable reordering techniques. Path balancing has helped to counter the early propagation effect (EPE) to achieve a glitch free circuit design. Non-linear shift register has been used to generate the mask bits to avoid prediction of the mask bit, even if those should be occasionally uncovered. The design has been evaluated on many aspects such as glitch attack resistance, correlation / differential power analysis attack resistance, peak power variance, etc. and found to have satisfactory circuit performance while being highly robust to side channel attacks.

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential lines, supporting the Time Enclosed Logic protocol along with a DPL structure. The security provided by SC-DDPL has been firstly investigated in simulation on some basic logic gates, designed adopting a commercial 40nm CMOS technology. Simulated experiments have highlighted the capability of SC-DDPL gates to guarantee a high-level of security also in presence of extreme capacitive mismatch, exhibiting strongly reduced NED/NSD metrics, as well as a reduction of the FED, compared to a reference RTZ-based WDDL implementation. In order to compare the proposed logic against other state-of-the-art countermeasures we have implemented a 4bit PRESENT crypto-core adopting several logic styles, evaluating different security metrics on a 65nm Intel Cyclone-IV FPGA. Experimental results have confirmed that the SC-DDPL outperforms other gate-level countermeasures in terms of security metrics with a reasonable area and power consumption overhead.

Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing

Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.

Low-Latency Hardware Masking with Application to AES

During the past two decades there has been a great deal of research published on masked hardware implementations of AES and other cryptographic primitives. Unfortunately, many hardware masking techniques can lead to increased latency compared to unprotected circuits for algorithms such as AES, due to the high-degree of nonlinear functions in their designs. In this paper, we present a hardware masking technique which does not increase the latency for such algorithms. It is based on the LUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) technique presented at CHES 2014. First, we show 1-glitch extended strong noninterference of a nonlinear LMDPL gadget under the 1-glitch extended probing model. We then use this knowledge to design an AES implementation which computes a full AES-128 operation in 10 cycles and a full AES-256 operation in 14 cycles. We perform practical side-channel analysis of our implementation using the Test Vector Leakage Assessment (TVLA) methodology and analyze univariate as well as bivariate t-statistics to demonstrate its DPA resistance level.

Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks

In this paper, binary decision diagram (BDD)-based dual-rail precharge logic circuit schemes have been developed to counter differential power analysis attacks, timing attacks, and early propagation attacks. Different precharge logic schemes (top precharging, top-bottom precharging, bottom precharging, and symmetric nMOS bottom precharging) are presented and evaluated. The hallmark of our circuit schemes is that an identical number of switchings is ensured on each circuit path. The transistors are interconnected to create pull-up and pull-down paths to outputs by way of binary decisions based on the input variables, so as to realize the required Boolean function. A simple synthesis algorithm for mapping a given Boolean function to such a BDD-based circuit is also presented. Experimentation has been carried out on two 4-, 16-, 32-, and 64-bits S-boxes to establish resistance of our circuits to power analysis attack and to highlight the low-power characteristics with the help of attributes such as peak power variance, average power, propagation delay, normalized standard deviation of power, and normalized energy deviation. Differential power attacks such as difference of mean and correlation power analysis have been carried out. Resilience to the early propagation effect is also demonstrated.

TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results

This paper presents experimental results on a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions. The proposed logic family is based on the time enclosed logic (TEL) encoding and can be viewed as an improvement of the delay based dual rail pre-charge logic (DDPL) logic style. The DDPL logic gates have been redesigned to avoid the early evaluation effect and to reduce area and power consumption. A library of TEL secure gates and flip-flops has been implemented in a 65 nm CMOS process. The developed library allows adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. A four bit lightweight crypto core has been implemented on a 65 nm CMOS testchip by using the developed TEL library and compared against a SABL implementation of the same crypto core on the same chip. Comparisons have been carried out by means of extensive transistor level simulations and measurements on the 65 nm testchip which allowed to evaluate a wide set of security metrics. Experimental results have shown a strong reduction of the information leakage with respect to the sense amplifier based logic logic style under mismatched load conditions with an improvement in the measurements to disclosure of more than three orders of magnitude.

Dynamic current mode logic based flip‐flop design for robust and low‐power security integrated circuits

Side-channel analysis (SCA) is a powerful technique to reveal the secrets using detectable physical leakages from logic elements, which brings severe security threats to modern circuits. To alleviate this problem, applying cell-level countermeasure is usually a suitable solution, which is mainly implemented as dual-rail precharge logic. Mace et al. has the proposed dynamic current mode logic (DyCML) scheme as a novel technology to resist SCA, whose power consumption is constant regardless of the data processed. However, the DyCML-based sequential elements are still in blank field. So, we have implemented a novel flip-flop compatible with DyCML, whose enhanced security has been proved by corresponding simulations.

RES eliminated fault detection

ABSTRACTThe read or write operation on a core cell imposes a stress on the unselected core cells of that row, which is equivalent to that of a read operation. Such stress on the unselected core cell is termed as Read Equivalent Stress (RES). Considering RES principal, the power dissipation becomes very important constraint during fault testing of Static Random Access Memories (SRAMs) using March Tests. In order to minimise the power dissipation during testing of SRAMs, it has been found that the power consumption associated with RES is wholly unnecessary and is focused to be completely eliminated in our work. The novel RES Eliminating Pre-Charge Control Logic has been proposed to eliminate RES which exploits the fact that during test, the addressing sequence of SRAM is known well in advance. The proposed RES Eliminating Pre-Charge Control circuit ensures the complete elimination of RES as well as of power dissipation contributed by RES during test of SRAM. We have observed and analysed that the proposed RES Eliminating Pre-Charge activity produce none of the RES during test for different March algorithms.

Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic

As lithographic feature sizes approach fundamental scaling limits, a variety of computational domains remain incompatible with integrated circuits merely due to their operating principles. Resonance energy transfer (RET) logic offers a molecular-scale solution for accessing these untapped domains. This emerging technology uses self-assembled networks of fluorescent molecules to perform computation at scales far below the diffraction limit and in environments that preclude silicon electronics. In this article, the authors propose a new form of RET logic design that yields a library of nonlinear logic gates that can be cascaded to build more complex integrated molecular circuits.

Redefining the transparency order

In this paper, we consider the multi-bit Differential Power Analysis (DPA) in the Hamming weight model. In this regard, we revisit the definition of Transparency Order ($$\mathsf {TO}$$TO) from the work of Prouff (FSE 2005) and find that the definition has certain limitations. Although this work has been quite well referred in the literature, surprisingly, these limitations remained unexplored for almost a decade. We analyse the definition from scratch, modify it and finally provide a definition with better insight that can theoretically capture DPA in Hamming weight model for hardware implementation with precharge logic. At the end, we confront the notion of (revised) transparency order with attack simulations in order to study to what extent the low transparency order of an s-box impacts the efficiency of a side channel attack against its processing. To the best of our knowledge, this is the first time that such a critical analysis is conducted (even considering the original notion of Prouff). It practically confirms that the transparency order is indeed related to the resistance of the s-box against side-channel attacks, but it also shows that it is not sufficient alone to directly achieve a satisfying level of security. Regarding this point, our conclusion is that the (revised) transparency order is a valuable criterion to consider when designing a cryptographic algorithm, and even if it does not preclude to also use classical countermeasures like masking or shuffling, it enables to improve their effectiveness.

SRAM Cell Memory Design for Power Reduction using Low Power Techniques

SRAM memory cell consists of many input signals like precharge, write enable, sense amplifier enable, read enable and row and column encoders. To develop a novel SRAM design, different transistor circuits are available. Normally SRAM cell uses conventional 4 transistor circuit in low power applications. In this thesis, instead of conventional circuit, 8 transistor (8T) and ten transistor(10T) designs are tried to improve the power efficiency under various temperature conditions. Initially 8T and 10T SRAM circuits are designed with write driver logic and the power is calculated for both static and dynamic conditions. Then, charge recycling logic is tried along with precharge logic with various temperature ranges. From the design, total power, static power, dynamic power, Transient time, transient delay and static current in 8T SRAM and 10T SRAM cell are calculated and compared. The 8T SRAM has the least transistor count and least area efficient, but speed of operation is somewhat reduced. Further, increase in the transistor count in 10T SRAM cell, however, makes area and delay large in room temperature. When temperature increases from a particular value, the 10T SRAM cell performs better than the 8T SRAM cell. This justifies the use of 10T SRAM cell for low power applications with varying temperature conditions. The proposed SRAM memory design can be implemented in any digital circuit.

A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis

A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis

Exploiting FPGA Block Memories for Protected Cryptographic Implementations

Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail precharge logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

A Charge Recycling Three Phase Dual Rail Pre-Charge Logic Based Flip-Flop

A Charge Recycling Three Phase Dual Rail Pre-Charge Logic Based Flip-Flop

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This article describes our novel masked dual-rail pre-charged memory approach, called “intra-masking dual-rail memory (IMDRM) on LUT”, and its implementation on FPGA for Side-Channel Attack-resistant (SCA-resistant) AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and parts of dual-rail memory with unsafe buses (buses that are not masked) are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. Inputs and outputs of all LUTs are masked, and so can be considered safe signals. Several LUTs can be combined to create a safe SBox. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced SCA-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic

Dual-rail Precharge Logic (DPL) has been widely studied as an effective countermeasure category for mitigating Side Channel Attack (SCA) threats, where unwanted physical leakages from running crypto devices are inspected and analyzed to retrieve confidential data. DPL protocol requires compensated behavior between the corresponding rails, which differs from conventional logic principles. Thus it needs unusual design flows with repetitive and tedious workload. In this article, we present a custom execution tool to automatically realize a dual rail logic. This controllable and automated design flow relies on Xilinx FPGA platforms, to obtain dual rails with highly symmetric networks. The tool is able to automate the logic transformation from a raw single rail on Xilinx Design Language (XDL) to the Precharge Absorbed DPL (PA-DPL) format. Users can fully or partially convert the circuit in arbitrary placement schemes, without concerning the routing conflicts. Another significance is that this proposal is potentially to be used to other circuits that require precise routing control. SCA Security verification to an 8-bit AES coprocessor on SASEBO-GII indicates enhanced security grade due to the rigorous routing networks achieved by the repair process. Timing analysis further demonstrates that the net delay differences between complementary nets are minimized.

A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family

This paper investigates the design of a data flip-flop compatible with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption, an additional discharge phase is performed after pre-charge and evaluation. In this work, the TDPL basic gates operation is shortly summarized and the TDPL flip-flop implementation is reported. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption balancing in excess of 10 times with respect to the state of the art.