Side-channel attack–resistant PRESENT cipher by versatile key scheduling and compact S-box utilizing optimized three-phase logic design

Abstract

The most widely used technology at the moment is the Internet of Things (IoT), which is expanding at a rapid pace because it allows us to remotely control and manage a variety of smart devices and relieves us from our demanding daily routines. Technology is also vulnerable to security breaches, as evidenced by the rise in cybercrimes and identity theft. More so than any other known IoT security breach, side-channel analysis is extremely insecure. A current issue for lightweight IoT applications is differential power analysis, a kind of side-channel analysis that is very accurate in obtaining the secret key. As a result, developing a safe style takes more time and effort. PRESENT is an easy-to-use, low-power encryption algorithm that is based on Advanced Encryption Standard (AES) and is utilized in IoT devices like RFID tags and access cards. Even with the plethora of countermeasures proposed in the last ten years, none are able to keep up with the IoT’s rapid expansion. A clever combination of masking and hiding techniques could stop several security breaches. Masked three-phase dual rail pre-charge logic is a new hybrid countermeasure that thwarts combined side-channel attacks and is suggested as a means of attaining the necessary degree of security. The hybrid design utilized in PRESENT resulted in an increase in complexity and required more work in terms of area and power. Consequently, more PRESENT optimization techniques are applied. Additionally, for PRESENT hardware implementation, a flexible key scheduling structure with parallel input and output is proposed. Using the Cadence Virtuoso simulation tool with 180-nm technology, a secured structure combining optimized algorithm and secured logic is designed, and the outcomes are analyzed. Normalized energy deviation (NED)/normalized standard deviation (NSD) analysis and Pearson correlation are used to analyze safety. The simulation results for the gates show that our proposed logic has the lowest values of NED and NSD at the assigned frequencies. When compared with side-channel analysis, the outcomes have shown to be both safe and effective. In comparison to earlier designs, the suggested system’s area and power consumption are cut by 67% and 64%, respectively.