Precharge Level Research Articles

Effect of varying cycle time interval and aerosol pre-charge on filtration performance of polyester media

Present study embodies filtration characterization of two nonwoven needle-felt polyester filter materials, viz. PTFE coated and without coated media. The materials have been assessed using flyash aerosol under varying time intervals (6, 9 and 12 min) at different inlet dust densities (50, 90 and 150 g/m3). The flyash particles are charged prior to their deposition over the filter media using a three phase parallel plate box pre-charger at two different levels of pre-charge, viz. 4 kV and 8 kV along with 0 kV. Results reveal that the filtration performance for PTFE coated material is better under all conditions. However, an enhanced filtration performance in terms of particle emission and pressure drop is noted at increased pre-charge level and higher cyclic interval. It may also be noted that the level of improvement in filtration behavior for both the materials has been better at initial level of pre-charge from 0 kV to 4 kV. However, the cumulative behavior of all the factors is also found significant.

Power Consumption Analysis of Pulse Jet Filtration System Assisted with Pre-charger using Polyester Conductive Media

Energy consumption is a vital aspect for any industry considering the cost-effective aspect. The current study embodies the power consumption during filtration of conductive filters at different dust pre-charging levels on laboratory-based pulse jet tubular set up assisted with pre-charger. Three types of polyester conductive non-woven filter materials, viz. PTFE-coated media, stainless steel fibre blended with PET media and stainless steel scrim media, have been characterized at three different charge levels, viz. 4 kV, 8 kV, 12 kV, and without charge. The outcome revealed that there has been a significant drop in power consumption with the rise in pre-charge level. Energy utilization results have further been compared with full-scale bag house condition by calculating the energy consumed for 50 bags. The results showed that among all the materials taken for investigation the performance of PTFE-coated media is the best and role of material is most significant towards the energy consumption by the filtration system. Overall energy consumption decreases with rise in pre-charging level. It is observed that percentage contribution of energy utilized for fan has been much higher for full-scale bag house as compared to tubular-based set-up. However, in case of energy consumed by the compressor, the difference in percentage contribution is relatively less and for energy utilized due to charge, not much variation in contribution can be noted.

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM

A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85–5.88 times and 35%–70%, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9%.

Performance optimization of 1T-1C DRAMs: A quantitative study

There is no doubt that the one-transistor one-capacitor dynamic random-access memories (1T-1C DRAMs) play the most important role as the main memory in several volatile storage systems. The performance of this type of memories is dependent to a large extent on the size of the cell-storage capacitor, Cs, the bitline-parasitic capacitance, CBL, and the bitline precharge level, Vpre. In this paper, the performance of such memories will be evaluated by a proposed figure of merit (FOM) that takes into account the area, the sense margin, the average power consumption, and the average cycle time in the entire memory chip. A quantitative analysis will be performed in order to derive a compact form for the proposed figure of merit. This figure of merit will be evaluated for a certain technology and for certain ranges of Vpre, Cs, and CBL with the optimum values of these parameters determined. The impact of technology scaling on the performance of the 1T-1C DRAM will also be investigated. The derived expressions for the read-access time and the power consumption will be compared with the simulation results for the 45nm CMOS technology with VDD=1V.

Fast CR-SRAM Using New Charge-Recycling Scheme

In this paper, a CR-SRAM using new charge recycling scheme is described, novel bit-line pre-charge voltage distribution is proposed. The SRAM pre-charge voltage level is designed by logarithm instead of linear. The new design leads to improvement in speed compared to the original CR-SRAM. Simulation results show that the new CR-SRAM using novel pre-charge voltage distribution scheme reduced the write access time by 34% with 9% power dissipation penalty.

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

Abstract. The conventional sensing scheme of single-ended read-only-ports as integrated in 8T-SRAM cells suffers from low performance compared to double-ended complementary sensing schemes. In the proposed sensing scheme the pre-charge voltage of the single-ended read-bit-line is set to a level above the threshold voltage of the sensing device with an adjustable margin. This margin is minimized to speed up the read access on the one hand and kept large enough to provide a sufficient bit-line noise margin on the other hand. The pre-charge voltage level of the proposed sensing circuit tracks the threshold voltage of the sensing device under process variations in order to maintain a minimum required bit-line noise margin. To avoid unnecessary bit-line discharging, the proposed sensing scheme employs a modified 8T-SRAM cell. Compared to the conventional 8T-SRAM cell, the read port of the proposed cell provides a virtual ground line running in parallel to the bit-lines. An internal driver of the sensing circuit releases the virtual ground line during the evaluation period to prevent the charge dissipation resulting in a raised voltage level. The reduced pre-charge level and the increased virtual ground lead to a reduced bit-line voltage swing and thus a bit-line power reduction. Access time, energy dissipation, and noise margin of the proposed sensing circuit are compared with conventional sensing circuits from the literature for different numbers of memory cells connected to the bit-line. It is shown, that for a specific number of memory cells per bit-line the proposed circuit achieves fastest access time at low power operation.

1 Gb/s, 50 .MU.m * 50 .MU.m Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling

A capacitive coupling wireless connector circuit is implemented with 50µm × 50µm pads, which is a 25X reduction of pad size compared with previous wireless connectors by allowing contacting and non-contacting modes. The proposed track and charge scheme allows both contacting and non-contacting communication through PCB capacitive pads. By making the precharge level of the input VDD or VSS, instead of 1/2VDD, the time necessary to precharge is reduced. The proposed digitally tunable comparator does not require analog voltages, reduces the power to less than 1/20 at lower frequencies compared to previous capacitive coupling receivers. A test chip successfully transmitted and received 1Gb/s, 27-1PRBS signal at 1mW while increasing design freedom of the wireless connectors.

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses

A guarantee obligation of keeping a Static-Noise-Margin (SNM), a Write-Margin (WRTM), and a cell current (Icell) even against a simultaneous Read/Write (R/W) disturbed access at the same column is required for a 1R/1W (1R/1W) SRAM. We have verified that it is difficult for the previously proposed techniques [1]-[5] so far to meet all the requirements simultaneously without any decrease in Icell or any significant area penalty. In order to address this issue, a new cell design technique for the 1R/1W SRAM cell with 8Tr's has been proposed and demonstrated in a 65 nm CMOS technology. It has been shown that Icell in the R/W disturbed column can be increased by 77% and 195% at V dd =0.9 V and 0.6 V, respectively, and a cell size can be reduced by 15%, compared with the conventional column-based cell power-terminal bias (VDDM) control [1], [2] assuming that the same Icell of 9 μA at V dd =0.9 V has to be provided. Compared with the conventional scheme, it has been found that the proposed Write-Bit-Line precharge level (VWBL) control and column-based cell source-terminal bias (VSSM) control can provide a 1.45-times larger SNM for Write-Word-Line (WWL) disturbed cells and a 1.7-fold larger WRTM while keeping the same Icell, respectively.

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die size and a 0.044-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.

Boosted charge transfer preamplifier for low power Gbit-scale DRAM

A new charge transfer preamplifier scheme is developed for low power and high density DRAMs. It employs a boosting method with a MOSFET capacitor for a high voltage precharge level and a pulse control signal for a charge transfer switch. The new scheme increases the sensing margin and enhances the sensing speed under 1.5 V operation with a small area overhead. It also leads to a wider design window for a charge transfer switch as the supply voltage scales down.

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

A charge-share modified (CSM) precharge-level architecture for selective subdataline activation designed to simultaneously achieve high-speed and low-power ferroelectric nonvolatile memories is described. In this architecture, to read the data of only one memory cell destructively, the precharge level of the selected subdataline is modified by charge-sharing between the subdataline and main dataline. This architecture enables high-speed read operations, because the operations of modifying the precharge level and reading the data of memory cells are achieved simultaneously. Three circuit technologies are used in the CSM architecture to increase the operating margin: self-timing precharge circuits which solve the polarization disturbance problem without adding extra signal lines or timing margins, a boosted precharge level technique which increases the signal voltage of the nonvolatile data, and shared dummy cell circuits which improve the precision of the reference voltage over that of a conventional voltage generator. These techniques and circuits are evaluated for a simulated 16-Mb ferroelectric memory. They reduce the access time by 20 ns to 51 ns compared with the conventional architecture, while reducing the memory array current to less than 1% that of the all-subdataline activation technology.

A current direction sense technique for multiport SRAM's

This paper describes two techniques for low-power single-end multiport SRAMs: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal, When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%.

Large-signal 2T, 1C DRAM cell: signal and layout analysis

This paper presents a general signal and layout analysis for the two-transistor, one-capacitor DRAM cell. The 2T, 1C configuration enables significantly larger, typically /spl gsim/3x, raw sense-signal than is achievable in conventional 1T, 1C cells. In general, stray capacitances at the capacitor nodes further increase the signal level; an exact analytic formula is derived in this case, including the dependence upon bitline precharge level. With trench technology, the 2T, 1C cell occupies 25-30% more area than a corresponding folded-bitline 1T, 1C cell; an implementation employing a buried strap is proposed. Maximization of array density requires multiplexing bitlines to sense amps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures

A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-/spl mu/m CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>