The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

Abstract

A charge-share modified (CSM) precharge-level architecture for selective subdataline activation designed to simultaneously achieve high-speed and low-power ferroelectric nonvolatile memories is described. In this architecture, to read the data of only one memory cell destructively, the precharge level of the selected subdataline is modified by charge-sharing between the subdataline and main dataline. This architecture enables high-speed read operations, because the operations of modifying the precharge level and reading the data of memory cells are achieved simultaneously. Three circuit technologies are used in the CSM architecture to increase the operating margin: self-timing precharge circuits which solve the polarization disturbance problem without adding extra signal lines or timing margins, a boosted precharge level technique which increases the signal voltage of the nonvolatile data, and shared dummy cell circuits which improve the precision of the reference voltage over that of a conventional voltage generator. These techniques and circuits are evaluated for a simulated 16-Mb ferroelectric memory. They reduce the access time by 20 ns to 51 ns compared with the conventional architecture, while reducing the memory array current to less than 1% that of the all-subdataline activation technology.