Pre-amorphization Implantation Research Articles

A comparative study of C, N and Xe pre-amorphization implantation processes for improving the thermal stability of NiSi films

In this paper, a comparative study of C-, N- and Xe-based pre-amorphization implantation (PAI) processes is proposed. The impact of the use of such processes on the agglomeration resistance and physical properties of the final Ni(Pt)Si layer, as well as the formation mechanisms via solid-state reactions and electrical performances via the transfer length measurement (TLM) method, is evaluated. It is shown that although all species are able to increase the agglomeration temperature of Ni(Pt)Si layers (up to more than 100 °C), the underlying mechanisms are different. For C- and N-based PAI processes a strong chemical effect is observed, while for Xe-based processes the amorphization depth plays an important role. Consequently, the beneficial effect of stabilizing Ni(Pt)Si layers at high temperatures using C- and N-based PAI processes has to be balanced with an increased layer resistivity (up to 30%) combined with a strong deterioration of the associated specific contact resistivity (which is multiplied by almost a factor 10). In this sense, Xe-based PAI processes seem to be a better option as they could allow to combine both requirements.

Nanoscale effect on the formation of the amorphous Ni silicide by rapid thermal annealing from crystalline and pre-amorphized silicon

The Ni monosilicide alloyed with Pt is widely used as contact material in advanced microelectronics devices and a good knowledge of silicide formation kinetics is required for the process control. In this work, the nature, and the growth kinetics of the first silicide obtained during the solid-state reaction between the Ni0.9Pt0.1 and the Si are studied for different pre amorphization implant (PAI) conditions as well as for a reference sample without PAI. Reactions between a 10 nm thick Ni0.9Pt0.1 film and Si (100) substrate are analyzed after several rapid thermal anneals (RTA). The nature of the first silicide is determined by Fourier Transform of TEM images and by chemical TEM-EDX analyses. The silicide growth behavior is determined by measuring the silicide thickness by X ray reflectivity (XRR) after the partial reaction induced by RTAs at different temperatures and times. To determine the growth law, the linear parabolic model is first considered but a nonlinear reactive diffusion model must be developed to accurately reproduce the experimental results. From this model, the effective diffusion coefficient as well as its activation energy were determined for the three samples with PAI and the reference sample without PAI. The influence of the driving force on the nonlinear diffusion for thin films is proved, and the impact of the amorphous substrate on the kinetics parameters is quantified and compared to the literature.

Influence of dual Ge/C pre-amorphization implantation on the Ni1−xPtxSi phase nucleation and growth mechanisms

The impact of dual Ge/C pre-amorphization implantation (PAI) processes on the Ni0.9Pt0.1(7 nm)/Si system phase sequence has been investigated by advanced X-ray diffraction techniques and transmission electron microscopy (TEM). Using a high carbon implantation dose, it is found that the expected development of Ni-rich phases is not observed: a thick amorphous Ni1−xPtxSi layer developed until Ni0.9Pt0.1 full consumption, followed by the development of a thin crystalline Ni1−xPtxSi layer along the TiN interface. By increasing the temperature further, this last one abruptly thicken, creating the final silicide layer. An alternative model to grain boundary diffusion is discussed, accounting for the final distribution of the foreign species within the silicide layer. The use of Ge in dual Ge/C PAI processes is proposed to impact the growing mechanisms by alloying to fine-tune the carbon distribution in the substrate sub-surface.

Ultrashallow Junction (USJ) Fabrication by Advanced Ion Implantation Processes

For advanced CMOS device process, a preamorphization implant (PAI) procedure had been carried on source and drain (SD) lightly doped source and drain (LDD), heavily doped source and drain (HDD), and contact implants before an ultralow energy (ULE) beamline (BL)-based implant to depress the channeling effect for lower OFF-current and short channel effect (SCE). One-step plasma doping (PLAD) was utilized to replace this two-step BL implant process for the pMOS device because PLAD has an in situ real-time controllability for less channeling effect. The PLAD using B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> gas with ULE high dose regime was utilized for this application. It significantly reduces cost and increases throughput because this one low-cost PLAD module eliminates PAI BL implant. The pMOS devices also exhibit significant performance improvements, including ~30% lower contact resistances ( <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</sub> ), similar threshold voltage ( <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and subthreshold voltage (SV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) characteristics, and ~8% higher drive currents (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DS</b></sub> ) without degrading OFF-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ).

Experimental Investigation of As Preamorphization Implant on Electrical Property of Ti-Based Silicide Contacts

The impact of As preamorphization implant (PAI) on specific contact resistivity ( ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) is investigated for Ti-based Ohmic contacts on n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Si in this article. The ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> value of TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Si contacts is greatly improved with low-dose As PAI whereas this improvement is impaired with increased dose of As PAI. The ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> results from the joint effort of the reduction of effective Schottky barrier height (SBH) to electrons ( φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\text bn,eff</sub> ), retardation of Ti silicidation, and annihilation of end-of-range (EOR) defects. Besides, the interfacial microstructures of TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Si affect ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> , correlated with the post metal anneal (PMA).

Impact of Ge pre-amorphization implantation on Co/Co-Ti/n+-Si contacts in advanced Co interconnects

Co has been proposed as one of the most promising candidates to replace W or Cu in interconnects, where Co–Ti could be used as a single barrier/liner to prevent Co out-diffusion into dielectric and Si substrate as well as to enhance the adhesion property. In this paper, the material and electrical properties of Co/Co-Ti/n+-Si contacts with different compositions and thicknesses of Co–Ti, with and without Ge pre-amorphization implantation (Ge PAI) were investigated elaborately. Sheet resistance, phase formation, interfacial morphology and element distribution were comprehensively characterized in terms of four-point probe, X-ray diffraction and high-resolution transmission electron microscopy in combination with corresponding energy dispersive X-ray spectroscopy respectively. Meanwhile, the specific contact resistivity (ρc) was extracted using refined transmission line model structures, and it is found that Ge PAI is indeed beneficial in reducing ρc values in Co/Co-Ti/n+-Si contacts. With the assistance of Ge PAI, the lowest ρc value of 8.56 × 10−9 Ω cm2 is accomplished for Co/Co0.65Ti0.35/n+-Si contacts, which is a ∼47.8% reduction in contrast to that without Ge PAI.

Schottky barrier diodes isolated by local oxidation of SiC (LOCOSiC) using pre-amorphization implantation technology

In this paper, the local oxidation of SiC (LOCOSiC) isolation using pre-amorphization implantation technology is integrated into the 4H-SiC Schottky barrier didoes (SBD) fabrication to evaluate its isolation ability due to the high sensitivity of SBD to those defects induced by process. Using Ar plasma treatment, the barrier height can be centralized at ~1.1 eV with reduced variation, which lies in between commonly-used SBDs with Ti (1.0 eV) and Ni (1.2 eV), considering cut-in voltage, leakage and breakdown voltage (VBD). Furthermore, at high reverse bias (−200 V), the leakage of the SBDs isolated by LOCOSiC is only ~10−5 A/cm2 at room temperature, 200× lower than that of the SBDs isolated by deposited SiO2, because the smoother topography is beneficial to release the field crowding effect. The maximal VBD achieves 515 V only with simple field plate termination. The electric field simulation suggests that the thermally grown field oxide with better quality retards the breakdown at the edge of the metal pad on field oxide.

Specific Contact Resistivity Improvement by As Preamorphization Implantation for Ti-Based Ohmic Contacts on n+-Si

As preamorphization implant (PAI) for Ti-based ohmic contacts on n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Si is explored in this article. With As implantation at 3 keV/5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , the specific contact resistivity (ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) of TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> on 1.4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> P-doped (Nd) n+-Si is significantly reduced by ~33.8%, down to ~2.33 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> -cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . This ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> improvement is a result of manipulation between the reduction of effective Schottky barrier height to electrons (φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bn,eff</sub> ) and the retardation of Ti silicidation, which are both strongly correlated with As segregation. In comparison with the widely adopted Ge PAI, As PAI shows superior performance for nMOS contact engineering, featuring with lower ρ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> and φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bn,eff</sub> as well as better thermal stability.

Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40 μA/μm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressed at the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decade was obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

Impacts of Ge Preamorphization Implantation and Si Capping on the Specific Contact Resistivity of Ni(Pt)SiGe/p+-SiGe Contacts

This article explores the impacts of both Ge preamorphization implantation (PAI) and Si capping on the specific contact resistivity ( $\rho _{c}$ ) of Ni(Pt)SiGe/p+-SiGe contacts elaborately. Both Ge PAI and Si capping are found to be beneficial in reducing the $\rho _{c}$ of Ni(Pt)SiGe/p+-SiGe contacts remarkably, with $\rho _{c}$ values reduced from the original ${20.03} \times {10}^{-{8}} \Omega $ -cm2 to ${9.92} \times {10}^{-{8}}\,\,\Omega $ -cm2 with Ge PAI and ${1.44} \times {10}^{-{8}} \Omega $ -cm2 with Si capping, respectively. Improved interfacial uniformity and morphology are thought to be primarily responsible for such significant reductions in $\rho _{c}$ since neither Ge PAI nor Si capping induces an obvious difference in B concentrations at the interface of Ni(Pt)SiGe/p+-SiGe. Moreover, by combining Ge PAI or Si capping with extra B implantation before germanosilicidation to intentionally introduce B dopant segregation (DS) at the interface of Ni(Pt)SiGe/p+-SiGe contacts, further reduction of $\rho _{c}$ values is accomplished as anticipated.

Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations

ABSTRACTAs advanced CMOS scaling with FinFETs continues beyond the 10/7nm nodes, contact resistance (Rc) remains a dominant component affecting device performance. The FinFET Source/Drain (S/D) contact area has become smaller with fin pitch scaling, resulting in drastically increased Rc. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes, it is critical to continue to reduce contact resistivity (ρc) &lt; 1.0x10-9 Ω.cm2 for both NMOS and PMOS. In this paper, we review the recent trends for ρc reduction for advanced CMOS devices and discuss approaches that have demonstrated reduction in ρc, such as in-situ heavily doped epitaxial films for S/D, advanced ion implantation and laser anneals. The implant techniques include pre-amorphization implants (PAI), dopant boosting implants, cryogenic (-100°C) implants for damage engineering and plasma doping (PLAD) for conformal doping of high aspect ratio (HAR) contacts. With such high levels of doping from epi and implants, advanced laser anneals are key for epitaxial regrowth and formation of metastable alloys for dopant supersaturation or segregation in top layers. Millisecond laser anneal (MSA) improves dopant activation and nanosecond laser anneal (NLA) permits superactivation, and both have become key enablers for ρc reduction. This paper also reviews two alternative contact approaches: dual silicide scheme and wrap-around contact (WAC), as potential pathways to further reduce Rc for advanced CMOS nodes.

Exploration of the impact of interface states density on the specific contact resistivity in TiSix/n+-Si Ohmic contacts through high-low frequency method

In our previous work, a reduction of specific contact resistivity (ρc) in TiSix/n+-Si Ohmic contacts by ∼21% has been achieved with proper Ge Pre-amorphization Implantation (PAI). In this work, the mechanism behind such an improvement using Ge PAI is explored experimentally. Versatile characterizations including current–voltage (I–V), capacitance–voltage (C–V) measurements and cross-sectional transmission electron microscopy (XTEM) are performed and analyzed. High-low frequency method is used to extract the responsive interface states density (Dit) of TiSix/n-Si Schottky diodes with and without Ge PAI. It is demonstrated that in TiSix/n+-Si Ohmic contacts, the ρc reduction by ∼21% with Ge PAI should be ascribed to the reduction of Dit at TiSix/n-Si interface. From the distribution of Dit, it can be inferred that a part of shallow level defects can be annihilated after annealing for TiSix/n-Si with Ge PAI, but deep level traps still exist. A further discussion about the relationship between Dit and ρc is tentatively provided.

Performance Improvement by Cold Xe Pre-Amorphization Implant for Nickel Silicidation of 28-nm PMOSFET

The cold Xenon pre-amorphization implant (Xe PAI) for nickel silicidation of 28-nm PMOSFET is investigated in this letter. For the first time, it is demonstrated that compared with the cold Si PAI, the cold Xe PAI can significantly reduce the global variation of threshold voltage, the OFF-state leakage, and the 1/ ${f}$ noise, but with yield improvement. The improvement is attributed to the uniform amorphization with the reduced defects and a flat nickel silicide/substrate interface induced by cold Xe PAI.

Improved Ti germanosilicidation by Ge pre-amorphization implantation (PAI) for advanced contact technologies

In this work, a fundamental material's study of the formation of ultrathin TiSixGey film on highly B-doped SiGe substrates with different Ge pre-amorphization implantation (PAI) conditions is presented, for its future application in Ti/p+-SiGe Ohmic contacts. The sheet resistance (Rsh), phase identity, morphology, as well as the elemental distribution for resulting TiN/Ti/TiSixGey stacking films were characterized using four-point probe measurements, X-ray diffraction (XRD), cross-sectional scanning transmission electron microscopy (STEM) in conjunction with electron energy loss spectroscopy (EELS), and Secondary Ion Mass Spectrometry (SIMS). It is found that Ti germanosilicidation process is significantly promoted by Ge PAI in employed temperature span of 400–600 °C. Across as-formed ultrathin TiSixGey films, the composition is not constant but graded from Ti-rich at Ti/TiN side to Si-rich at SiGe substrate side. The inhomogeneous interfacial layer consisting of crystallites with obvious lattice texture at TiSixGey/p+-SiGe interface is much thicker for the sample with Ge PAI than for the reference without Ge PAI. The percentage contents of Si and Ge in as-formed TiSixGey film with Ge PAI are much higher and lower than those without Ge PAI respectively. With Ge PAI, out-diffusion of B atoms towards TiSixGey films is more aggravated compared to the reference without Ge PAI.

Impact of Ge Preamorphization Implantation on Both the Formation of Ultrathin TiSi&lt;italic&gt;x&lt;/italic&gt; and the Specific Contact Resistivity in TiSi&lt;italic&gt;x&lt;/italic&gt;/n-Si Contacts

In this paper, the impact of different Ge preamorphization implantation (PAI) conditions on the formation of ultrathin TiSi x as well as on the specific contact resistivity ( $\rho _{c}$ ) in TiSi x /n-Si contacts was investigated systematically. Extensive material characterizations, such as cross-sectional transmission electron microscopy, X-ray diffraction, and angle-resolved X-ray photoelectron spectroscopy, as well as electrical characterizations such $\rho _{c}$ values, Schottky barrier height (SBH), and leakage current of p-n junctions, were performed. It is found that Ge PAI indeed promotes Ti silicidation at 550 °C and the resultant ${t}_{\text {TiSix}}$ values are strongly dependent on the thickness of amorphous Si ( ${t}_{\boldsymbol {\alpha -{\mathrm{ Si}}}}$ ) created by Ge PAI. The stoichiometry of TiSi x films is rather graded than constant from the TiN/Ti side to Si side. Proper Ge PAI is beneficial in reducing the $\rho _{c}$ values in TiSi x /n-Si contacts, and this reduction in $\rho _{c}$ cannot attribute to the reduction of SBH. Though proper Ge PAI leads to reduced $\rho _{c}$ values, the leakage current of p-n diodes is increased as a penalty which needs to be compromised in practical applications.

OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon–Germanium Channel pFET

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ( $\text{V}_{T}$ ) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage ( ${I}_{ \mathrm{\scriptscriptstyle OFF}} $ ) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages.

Impact of Ge pre-amorphization implantation on forming ultrathin TiGex on both n- and p-Ge substrate

In this work, the effects of Ge pre-amorphization implantation (PAI) on forming ultrathin TiGex films at 350–600 °C are explored. It is found that the Ge PAI indeed enhances the formation of TiGex at relatively low temperature, as confirmed by the lower sheet resistance and thicker TiGex films compared to the case without Ge PAI. The energy dispersive X-ray spectroscopy (EDX) reveals that the composition of as-formed TiGex across its thickness is rather graded than constant. Characterizations using advanced autocorrelation function (ACF) in transmission electron microscopy (TEM) demonstrate that numerous Ti6Ge5 and Ti5Ge3 nanocrystals are embedded in as-formed amorphous TiGex film.

Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology.

Improved leakage current and device uniformity for sub-20 nm N-FinFETs by cryogenic Ge pre-amorphization implant in contact

Prior to contact silicide formation, cryogenic Ge pre-amorphization implantation (PAI) was adopted in sub-20nm FinFETs to investigate how device characteristics can be affected. As compared to room-temperature PAI, cryogenic PAI does not enhance drive current from the viewpoint of mean value, however, it significantly improves variation in device parameters such as sub-Vt swing (SS), drain induced barrier lowering (DIBL) and total series resistance (RTotal) for N-FinFETs by 22%–34% which is due to a reduced number of end of range (EOR) defects caused by Ge PAI. However, the benefit is not observed for P-FinFETs since its source/drain is composed of SiGe which is intrinsically less prone to form EOR defects. In addition, cryogenic PAI also contributes to leakage current reduction for N-FinFETs including gate induced drain leakage (GIDL) by 67%, sub-Vt leakage by 50% and junction leakage by 67% which is primarily due to a lower number of EOR defects that make fewer native point defects. The mechanism for pronounced GIDL reduction for I/O devices than core devices is also proposed. Besides the improved device uniformity as well as leakage current, the process can be fully integrated into incumbent VLSI technology and holds great potential for sub-10nm node.

Optimization of Ni(Pt)/Si-cap/SiGe Silicidation for pMOS Source/Drain Contact

The Ni(Pt)/Si-cap/SiGe silicidation process has been optimized by modulating the Si-cap layer thickness and a cold Si preamorphization implantation (PAI), which effectively reduces the sheet resistance (Rs). In addition, it is revealed that PAI can obviously increase the Ni(Pt)Si grain size for a lower Rs.