Power Tradeoffs Research Articles

Application of Ultrasonic Thermography in the detection of delamination in the Glass Fiber Reinforced Plastics

In the present research, the applicability of active thermography using ultrasonic excitation in detecting delamination defects has been investigated experimentally. In this regard, a Glass Fiber Reinforced Plastic (GFRP) Sample was prepared via the hand layup method. PTFE sheet pieces were considered delamination defects located inside the sample. The delamination defects were considered in the three different sizes. Moreover, three delaminations with similar sizes were placed in three different depths. The ultrasonic excitations were conducted using a Piezoelectric PZT transducer. The excitation frequency was adjusted to a constant value. The ultrasonic thermography inspections were performed with three different excitation powers. The sample was constrained in the fixed-fixed mode. The thermography inspections were carried out with three various excitation times. Results indicated that the defect of a maximum size has been detected in all inspections. Moreover, in order to enhance the detectability a trade-off of excitation power and excitation time should be selected.

Effect of bit-size reduced half-precision floating-point format on image pixel characterization for AI applications

Image processing is an essential first step towards fully utilizing robotics, deep learning, and machine learning techniques. Using techniques like image enhancement, restoration, and segmentation are able to extract pertinent information from images and use it for task execution and decision-making. However, the hardware implementation of these algorithms demands more delay, area, and power. This work proposes a new mantissa bit-size reduced half-precision floating-point format for processing and characterizing image pixels for machine learning algorithms. In the realm of imaging, lowering the mantissa bit-size in floating-point can conserve area and power when utilized for internal calculations. Together with the area-power reduction, there is also a progressive reduction in image quality. For any image application, it becomes necessary to monitor the area and power trade-offs related to the amount of bits used to process the raw data. This work assists in selecting the bit-size for internal computations based on the accuracy requirements of the application by reporting the area, and power for various bit size reductions. The updated pixel values after applying the mantissa bit-size reduction are displayed in this study, along with a theoretical explanation of its inaccuracy. Since multipliers and adders are needed for the majority of mathematical equations in machine learning image algorithms, they are developed later in this work to process the image. The processed image is based on various adjusted pixel values, and the experimental findings demonstrate 75.2% to 21.3% area optimization, and 66.43% to 20.4% power optimization. However, determining the PSNR and MSE values of the processed image allows for quality validation.

Developing power plant materials using the life cycle lens.

The Spherical Tokamak for Energy Production (STEP) environment will include magnetic, thermal, mechanical and environmental loads far greater than those seen in the Joint European Torus campaigns of the past decade or currently contemplated for ITER. Greater still are the neutron peak dose rates of 10-6 displacements per atom, per second, which in-vessel materials in STEP are anticipated to be exposed to. Reduced activation and high-fluence resilience therefore dominate the materials strategy to support the STEP Programme. The latter covers the full life cycle from downselected compositions and new microstructural developments to irradiation-informed modelling and end-of-life strategies. This article discusses how the materials downselection is oriented in plant power trade-off space, outlines the development of an advanced ferritic-martensitic structural steel, describes the 'Design by Fundamentals' mesoscale modelling approach and reports some of the waste mitigation routes intended to make STEP operations as sustainable as possible.This article is part of the theme issue 'Delivering Fusion Energy - The Spherical Tokamak for Energy Production (STEP)'.

Performance optimization of latent heat storage device based on surrogate-assisted multi-objective evolutionary algorithm and CFD method

The design of fin structures and the formulation of heat conductivity enhancers have always been critical factors influencing the performance of latent heat storage devices. However, achieving the optimal parameters of fin structures and the fraction of heat conductivity enhancers when adjusting multiple parameters simultaneously remains a time-consuming and labor-intensive task. In this paper, a combination of machine learning methods and computational fluid dynamics (CFD) was employed to optimize the parameters of fin structures and the mass fraction of expanded graphite with minor computational resources and time costs, thereby obtaining a set of Pareto optimal latent heat storage (LHS) devices that simultaneously considers energy storage power and energy storage capacity. The combination essentially is a surrogate assistant multi-objective evolutionary optimization algorithm, which utilizes batch recommendation strategies to recommend multiple high-quality candidate solutions that achieve a balance between two conflicting optimization objectives in CFD simulations. This method significantly reduces the number of model iterations and saves the time and computational resources required for multi-objective optimization. The results showed that the proposed algorithm only required 80 cases of CFD calculations to obtain two well-fitted Gaussian process models, leading to a 91 % improvement in computational efficiency. According to the recommendations from the algorithm, the LHS device with 78 fins of 2.0 mm thickness and 20 % mass fraction of expanded graphite could achieve the optimal trade-off of energy storage power and energy storage capacity. Compared to the prototype, the energy storage power and total energy storage capacity increased by 46.7 % and 22.1 %, respectively. The method proposed in this study can provide guidance for the optimal configuration design of LHS devices.

“First was to sit down and bring our minds together”. A qualitative study on safer conception decision-making among HIV sero-different couples in Zimbabwe

Decision-making on childbearing and safer conception use in HIV sero-different couples involves an intricate balance of individual desires and perceived HIV acquisition risk. This paper addresses an important knowledge gap regarding HIV sero-different couples’ considerations and the relationship and power dynamics involved when deciding to use a safer conception method. Between February and June 2019, we conducted semi-structured in-depth interviews among 14 men and 17 women, representing 17 couples, who exited the SAFER study – a pilot study assessing the feasibility, acceptability and cost-effectiveness of a safer conception programme for HIV sero-different couples in Zimbabwe. All couples in SAFER were provided with a choice of safer conception methods and were followed for up to 12 months of pregnancy attempts and 3 months following pregnancy. While couples generally perceived their safer conception discussions to be easy and consensus-driven, the decision-making process also involved complex gender dynamics and trade-offs in relationship power, which resulted in differing interpretations of what constituted a joint or shared couple decision. Participants regarded effective couple communication as an essential component of and precursor to good safer conception conversations and requested additional training in couple communication. Couples relied on information from healthcare providers to kickstart their safer conception discussions. Safer conception programmes should address relationship power imbalances, promote effective couple communication and offer healthcare provider support to enable HIV sero-different couples to make informed choices about conception in a manner that upholds their safety and reproductive autonomy.

Statistical design and analysis of controlled human malaria infection trials

BackgroundMalaria is a potentially life-threatening disease caused by Plasmodium protozoa transmitted by infected Anopheles mosquitoes. Controlled human malaria infection (CHMI) trials are used to assess the efficacy of interventions for malaria elimination. The operating characteristics of statistical methods for assessing the ability of interventions to protect individuals from malaria is uncertain in small CHMI studies. This paper presents simulation studies comparing the performance of a variety of statistical methods for assessing efficacy of intervention in CHMI trials.MethodsTwo types of CHMI designs were investigated: the commonly used single high-dose design (SHD) and the repeated low-dose design (RLD), motivated by simian immunodeficiency virus (SIV) challenge studies. In the context of SHD, the primary efficacy endpoint is typically time to infection. Using a continuous time survival model, five statistical tests for assessing the extent to which an intervention confers partial or full protection under single dose CHMI designs were evaluated. For RLD, the primary efficacy endpoint is typically the binary infection status after a specific number of challenges. A discrete time survival model was used to study the characteristics of RLD versus SHD challenge studies.ResultsIn a SHD study with the continuous time survival model, log-rank test and t-test are the most powerful and provide more interpretable results than Wilcoxon rank-sum tests and Lachenbruch tests, while the likelihood ratio test is uniformly most powerful but requires knowledge of the underlying probability model. In the discrete time survival model setting, SHDs are more powerful for assessing the efficacy of an intervention to prevent infection than RLDs. However, additional information can be inferred from RLD challenge designs, particularly using a likelihood ratio test.ConclusionsDifferent statistical methods can be used to analyze controlled human malaria infection (CHMI) experiments, and the choice of method depends on the specific characteristics of the experiment, such as the sample size allocation between the control and intervention groups, and the nature of the intervention. The simulation results provide guidance for the trade off in statistical power when choosing between different statistical methods and study designs.

Behavioral carry-over effect and power consideration in crossover trials.

A crossover trial is an efficient trial design when there is no carry-over effect. To reduce the impact of the biological carry-over effect, a washout period is often designed. However, the carry-over effect remains an outstanding concern when a washout period is unethical or cannot sufficiently diminish the impact of the carry-over effect. The latter can occur in comparative effectiveness research, where the carry-over effect is often non-biological but behavioral. In this paper, we investigate the crossover design under a potential outcomes framework with and without the carry-over effect. We find that when the carry-over effect exists and satisfies a sign condition, the basic estimator underestimates the treatment effect, which does not inflate the type I error of one-sided tests but negatively impacts the power. This leads to a power trade-off between the crossover design and the parallel-group design, and we derive the condition under which the crossover design does not lead to type I error inflation and is still more powerful than the parallel-group design. We also develop covariate adjustment methods for crossover trials. We evaluate the performance of cross-over design and covariate adjustment using data from the MTN-034/REACH study.

A paradigm shift in analog applications through reconfigurable FET

This paper presents the radio frequency (RF) and linearity analysis of a dual dielectric (DD) reconfigurable FET (RFET) for a wide variety of analog applications. A RFET can either act as a MOSFET or a TFET based on the electric potential applied externally over source and drain regions. The impact of DD reduces ambipolar current to large extent. Hence, DD-RFET is a multi functional (MF) device that can be configured in such a way that superior analog properties can be obtained at reduced static power loss. We found that DD-RFET processes a threshold voltage (Vth)= 0.2 V, transconductance (gm) = 4 mS, and gain bandwidth product (GBP) = 0.4 THz in nMOSFET configuration, while Vth = 0.64 V and subthreshold swing (SS) = 34 mV/decade in nTFET configuration. Also, DD-RFET has a Vth= 0.14 V, gm = 0.3 mS, and GBP = 17 GHz in pMOSFET configuration, while Vth = 0.52 V and SS = 31 mV/decade in pTFET configuration. Hence, DD-RFET eases circuit design as this MF device helps to provide high performance and low power using multi threshold (MT) technology. Also, we found that MOSFET has better linearity at low bias voltage and as the gain increases with the supply, promotes noise and distortion in the output. However, TFET produces more stable results at higher bias voltage than MOSFET. Hence, there is a clear trade-off in active power and linearity exist in RFET designs.

Automatic Generation of Spatial Accelerator for Tensor Algebra

Tensor algebra finds applications in various domains including machine learning applications, data analytics and others. Spatial hardware accelerators are widely used to boost the performance of tensor algebra applications. It has a complex hardware architecture and rich design space. Prior approaches based on manual implementation lead to low programming productivity, making it hard to explore the large design space. In this paper, we propose Tensorlib, a framework for generating spatial hardware accelerators for tensor algebra applications. Tensorlib is motivated by the observation that, tensor dataflows can be expressed with linear transformations, and they share common hardware modules which can be reused across different designs. Tensorlib first uses Space-Time Transformation to explore different dataflows, which can compactly represent the hardware dataflow using a transformation matrix. Next, we identify the common structures of different dataflows and build parameterized hardware module templates. Our generation framework can select the needed hardware modules for each dataflow, connect the modules using a specified interconnection pattern, and automatically generate the complete hardware accelerator design. Tensorlib remarkably improves the productivity for the development and optimization of spatial hardware architecture, providing a rich design space with trade-offs in performance, area, and power. Experiments show that Tensorlib can automatically generate hardware designs with different dataflows for a variety of tensor algebra programs. Tensorlib can achieve 318 MHz frequency and 786 GFLOP/s throughput for matrix multiplication kernel on Xilinx VU9P FPGA, which outperforms the state-of-the-art generators.

Efficient IoT Big Data Streaming With Deep-Learning-Enabled Dynamics

Internet of Medical Things (IoMT) is igniting many emerging smart health applications, by continuously streaming the big data for data-driven innovations. One critical obstacle in IoMT big data is the power hungriness of long-term data transmission. Targeting this challenge, we propose a novel framework called, IoMT big-data Bayesian-backward deep-encoder learning (IBBD), which mines deep autoencoder (AE) configurations for data sparsification and determines optimal tradeoffs between information loss and power overhead. More specifically, the IBBD framework leverages an additional external Bayesian-backward loop that recommends AE configurations, on top of a traditional deep learning loop that executes and evaluate the AE quality. The IBBD recommendation is based on confidence to further minimize the regularized metrics that quantify the quality of AE configurations, and it further leverages regularization techniques to allow adjusting error–power tradeoffs in the mining process. We have conducted thorough experiments on a cardiac data streaming application and demonstrated the superiority of IBBD over the common practices such as discrete wavelet transform, and we have further generalized IBBD through validating the optimal AE configurations determined on one user to other users. This study is expected to greatly advance IoMT big data streaming practices toward precision medicine.

A 0.0022 mm² 10 bit 20 MS/s SAR ADC With Passive Single-Ended-to-Differential-Converter

This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC, such that it can convert single-ended input signals. As the SDC is passive, the overall solution is power-efficient compared to active SDC solutions, and is especially suitable for lower/medium resolutions. As opposed to active SDC solutions with a static bias current, the proposed switched-capacitor network only consumes dynamic power, such that its consumption scales linearly with the sampling frequency. This paper discusses the basic concept of the proposed scheme, and analyzes the impact of noise and other imperfections, describes the trade-offs for power and area, and discusses the consequences for the input driver. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$60~\mu \text{m}\,\,\times 36~\mu \text{m}$ </tex-math></inline-formula> .

A PVT tolerant latch in a 90-nm CMOS and performances under AC noise

ABSTRACT Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.

UAV Relay Assisted Cooperative Jamming for Covert Communications Over Rician Fading

Covert communication can hide the legitimate transmission from unauthorized eavesdropping. Benefiting from the deployment flexibility, unmanned aerial vehicles (UAVs) can be utilized to enhance communication confidentiality. In this correspondence, we consider a covert communication network with the aid of a full-duplex UAV relay, which is employed to help the transmission and confuse the warden. The warden adopts a radiometer to detect the covert transmission. We first find the optimal detection threshold and calculate the minimum detection error probability. Furthermore, a closed-form expression of outage probability via UAV relaying is derived over Rician fading. Then, a power optimization problem is formulated to maximize the effective convert throughput with covertness constraint. Numerical results illustrate that the cooperative jamming can disrupt the warden, and the optimal power tradeoff can guarantee the covert transmission effectively.

Optimization of elliptic curve scalar multiplication using constraint based scheduling

Elliptic Curve Cryptography is public key cryptography that features smaller keys, ciphertexts, and signatures and is faster than RSA at the same security level. Scalar multiplication is the main and the most compute-intensive operation in the generation of keys. Point Addition, Doubling and Inversion are the basic operations for scalar multiplication. Inversion is a very expensive operation as compared to multiplication, addition and squaring in the finite fields with an affine coordinate system. López-Dahab coordinates are the best alternative to reduce the inversion overhead in scalar computation. Area, Delay and Power trade-offs are the main constraints in hardware implementations of scalar multiplication. In this paper, optimization of elliptic curve scalar multiplication using constraint-based scheduling for the López-Dahab coordinate system is proposed. Data dependency graphs of point addition and doubling are modified for optimization of area and delay. The proposed architecture is implemented on Altera Stratix-II FPGA. The constraint is applied on the field multiplication operation and the considerable area is reduced. The proposed architecture computes scalar multiplication in 11.43 μs and takes 9856 ALMs. The performance comparison with state of the art shows that area is reduced by 41.21%, delay is reduced by 2.4% and Area-Delay-Product is improved.

PAAD (Partially adaptive and deterministic routing): A deadlock free congestion aware hybrid routing for 2D mesh network-on-chips.

Due to the increase in integrated circuit technology processing, there is intense flooding of transistors on Multi-processor System-on-chips, making communication a more complex and costly asset. To regulate communication in such a complex environment, Network-on-chip (NoC) came up as a versatile and inflating communication architecture for large SoCs. It tackled various on-chip communication problems and increased performance. It also provided a great power tradeoff for large-scale System-on-chips (SoCs). Routing plays a very vital role in NoCs performance. Routing should not cause any deadlocks in the network as it can degrade the performance. So deadlock-free routing has been and is instill a concern in NoCs. In this paper, we have introduced a novel deadlock-free congestion-aware routing namely PAAD (Partially adaptive and deterministic routing). It is a conjunction of partially adaptive and deterministic routing which switch with each other based on network congestion. Here we have divided a mesh into different diagonal zones and different algorithms are followed in each zone. When there is no congestion, deterministic routing is followed in each zone, and when there is congestion partially adaptive routing is followed. Hence it takes the advantage of both and enhances the overall efficiency. We have compared our model with different algorithms with regard to latency, throughput, and power performance factor for various traffic patterns. The results reveal that our algorithm performs best than the rest.

Effective Workload Allocation in Fog Device based on Power Consumption and Delay Tradeoff

Fog computing that emerges as an important paradigm, describes decentralized computing architecture between cloud and devices. It includes potential challenges, such as increase in traffic overhead, since all requests are sent to the main server that causes delay, which cannot be tolerated in delay sensitive applications and the usage of inappropriate scheduling causes high power consumption in fog device. These challenges must be overcome by employing effective workload. In this paper, in order to find effective workload allocation based on power and delay tradeoff various scheduling algorithms like SJF (Shortest Job First), FCFS (First Come First Served) and RR (Round Robin) are implemented in fog device and its power and delay trade off are analyzed in fog computing subsystem.

Redox-Active Metaphosphate-Like Terminals Enable High-Capacity MXene Anodes for Ultrafast Na-Ion Storage.

2D transition metal carbides and/or nitrides, so-called MXenes, are noted as ideal fast-charging cation-intercalation electrode materials, which nevertheless suffer from limited specific capacities. Herein, it is reported that constructing redox-active phosphorus-oxygen terminals can be an attractive strategy for Nb4 C3 MXenes to remarkably boost their specific capacities for ultrafast Na+ storage. As revealed, redox-active terminals with a stoichiometric formula of PO2 - display a metaphosphate-like configuration with each P atom sustaining three PO bonds and one PO dangling bond. Compared with conventional O-terminals, metaphosphate-like terminals empower Nb4 C3 (denoted PO2 -Nb4 C3 ) with considerably enriched carrier density (fourfold), improved conductivity (12.3-fold at 300 K), additional redox-active sites, boosted Nb redox depth, nondeclined Na+ -diffusion capability, and buffered internal stress during Na+ intercalation/de-intercalation. Consequently, compared with O-terminated Nb4 C3 , PO2 -Nb4 C3 exhibits a doubled Na+ -storage capacity (221.0 mAh g-1 ), well-retained fast-charging capability (4.9min at 80% capacity retention), significantly promoted cycle life (nondegraded capacity over 2000 cycles), and justified feasibility for assembling energy-power-balanced Na-ion capacitors. This study unveils that the molecular-level design of MXene terminals provides opportunities for developing simultaneously high-capacity and fast-charging electrodes, alleviating the energy-power tradeoff typical for energy-storage devices.

Swarm intelligence-based mono and multi-objective methods for sizing preamplifier circuits for biomedical applications

In this article, various high-performance optimisation algorithms are used to optimise circuit parameters: firstly in a modified double ended differential amplifier for area optimisation; and secondly in an adaptive recycling folded cascode amplifier to deal with noise power trade-off. These circuits are used as preamplifiers in neural ailment such as epileptic seizure recording systems. Amongst the various analogue design challenges in a preamplifier, minimum area consumption and a good noise power trade-off are the necessary pre-requisites which require consideration. Traditional circuit sizing methods are tedious and prone to human error, so an alternative method is necessary to auto-size the circuit parameters. In this work, single objective algorithms are implemented to minimise area in the circuit, where the whale optimisation algorithm convergences earliest. While the multi-verse multi-objective optimisation algorithm shows good performance to maintain the noise power trade-off. These results are evaluated and compared in MATLAB and Cadence environment.

Sub-30-fs Yb:YAG thin-disk laser oscillator operating in the strongly self-phase modulation broadened regime.

We experimentally investigate the limits of pulse duration in a Kerr-lens mode-locked Yb:YAG thin-disk laser (TDL) oscillator. Thanks to its excellent mechanical and optical properties, Yb:YAG is one of the most used gain materials for continuous-wave and pulsed TDLs. In mode-locked operation, its 8-nm wide gain bandwidth only directly supports pulses with a minimum duration of approximately 140 fs. For achieving shorter pulses, a Kerr-lens mode-locked TDL oscillator can be operated in the strongly self-phase modulation (SPM) broadened regime. Here, the spectral bandwidth of the oscillating pulse exceeds the available gain bandwidth by generating additional frequencies via SPM inside the Kerr medium. In this work, we study and compare different laser configurations in the strongly SPM-broadened regime. Starting with a configuration providing 84-fs pulses at 69 W average power at 17 MHz repetition rate, we reduce the pulse duration by optimizing various mode-locking parameters. One crucial parameter is the dispersion control which was provided by in-house-developed dispersive mirrors produced by ion-beam sputtering (IBS). We discuss trade-offs in average power, pulse duration, efficiency, and intra-cavity peak power. For the configuration operating at the highest SPM-broadening, we achieve a minimum pulse duration of 27 fs, which represents the shortest pulse duration directly generated by any ultrafast TDL oscillator. The corresponding full width at half maximum (FWHM) spectral bandwidth exceeds more than five times the FWHM gain bandwidth. The average output power of 3.3 W is moderate for ultrafast TDL oscillators, but higher than other Yb-based laser oscillators operating at this pulse duration. Additionally, the corresponding intra-cavity peak power of 0.8 GW is highly attractive for implementing intra-cavity extreme nonlinear optical interactions such as high harmonic generation.

Power optimisation of single phase clocked feedback D flip-flop for CDMA

ABSTRACT A low power flip-flop is demanding delay element in digital sigma delta modulator of DAC system. This paper highlights power optimisation of single-phase clocked feedback D flip-flop using various optimisation techniques like clock gating, MTCMOS etc. In this scenario, clock gating using GDI and single-phase clocked inverter is invented to avoid unwanted no data transitions of flip-flop, also proposed type is compared with existing techniques. In addition to this, full swing GDI (gate-Diffusion Input) cell itself is modified by single phase clocked inverter to minimise threshold voltage drop and unwanted spikes at the output. There is trade off in area, speed and power. This work is based on power optimisation with favourable speed and area. Flip-flop is verified for clock frequency of 50 MHz as well as CDMA (Code Division Multiple Access) frequency of 1.6 MHz. Analysis is carried out in SPECTRE simulator of CADENCE environment with 180 nm technology supplied by AMS. Not only power but delay is also measured to check the performance of flip-flop. Proposed circuit gives 92.8% power and power delay product improvement.