A PVT tolerant latch in a 90-nm CMOS and performances under AC noise

Abstract

ABSTRACT Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.