A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Abstract

Multiplexer (mux) latch is one of the key components for serializer interface to admit communication at Gbps. This work describes the working of a 2:1 mux-latch coupled to a power delivery network (PDN) and a CPU core drawing abrupt current. In comparison to conventional designs, multiplexer and latch operate at the same time, which is quite different because enable inputs are imperative to start latch operation. An analytical model is also derived to understand power delay trade-off and to choose gate sizes to obtain a comparable delay without increasing power. The average power and delay in post-layout are 257.7 μW and 35 ps, respectively, in a 90-nm CMOS, power supply voltage (Vdd) of 1.1 V and a clock switching at 6.25 GHz. However, a 117OC change in temperature at distinct corner allows average power to vary between 32.8 and 64 μW. The corresponding variation is 135–183.7 μW as Vdd switches from 0.75 to 1.1 V. In addition to so, delay changes between 5-14 ps and 3–12 ps for the given change in temperature and Vdd, respectively. Nonetheless, the effective supply voltage VP oscillates with time as the CPU core draws abrupt current. The delay values due to AC noise are found to be different than VP having no noise and the corresponding jitter changes linearly as a function of noise.