Abstract
This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
