Power Supply Ripple Rejection Research Articles

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the ΔVGS of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator

A tiny-size ultra-low voltage CMOS voltage reference operating at quiescent picoamp scale has been proposed in this paper to fit the high standards of modern wireless microsystems. Without any on-chip resistor or operational amplifier (opamp), the sensitive core of the proposed voltage reference is protected from the glitches of the power supply via a temperature-dependent cascode current source biased by the output. The upper limit of the output temperature range is broadened by the increased diode leakage current of the proposed current generator. The case study deals with implementation of the new circuit and post-layout simulation results in 0.18-μm CMOS technology. The circuit occupies an active area of 629 μm2, consuming almost 690 pA from 0.3 V minimum supply voltage at room temperature. The untrimmed 229 mV output voltage exhibits an average temperature coefficient (TC) of 47.39 ppm/°C over the −40 °C–140 °C temperature range. The line-voltage sensitivity (LS) is 0.17%/V when the input supply is varied from 0.3 V to 1.8 V, and can be improved by 9 × if the lower limit of the power supply is increased to 0.4 V. The DC power supply ripple rejection (PSRR) is lower than −80 dB for the line voltage beyond 0.5 V.

3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

A −40 °C to 140 °C Picowatt CMOS Voltage Reference With 0.25-V Power Supply

This brief presents a picowatt CMOS voltage reference with ultra-low supply and wide temperature range. Biased by PMOS leakage current, ultra-low voltage and ultra-low power consumption are achieved. The temperature range is enlarged by using the increased bulk diode leakage current modulation (BDLCM) effect at high temperature. The proposed design is implemented in a standard 0.18- μm CMOS process. The measurement results show that, the proposed circuit can provide an average voltage reference of 118.1 mV with a standard deviation of 1.3 mV. The minimum supply voltage is 250 mV and the line sensitivity (LS) is 0.3 %/V. The average temperature coefficient (TC) is 73.5 ppm/°C with a standard deviation of 11.7 ppm/°C within a temperature range from -40 °C to 140 °C. The power supply ripple rejection (PSRR) at 100 Hz is -65 dB. The power consumption at room temperature is 113 pW and the active area is 0.0009 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8 nW at 0.6 V supply. The active area is 0.019 mm2.

A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference

A dual-output CMOS voltage reference is presented for ultra-low power applications that require two or more different voltage references. The $\text{V}_{\mathrm{ REF1}}$ is designed by employing the $\text{V}_{\mathrm{ TH}}$ difference between two devices to compensate the temperature coefficient (TC) of the thermal voltage. The $\text{V}_{\mathrm{ REF2}}$ is generated by feeding a current mirrored from the first reference voltage’s supply current into a diode-connected-transistor load. In such a way, two different voltage references can be generated in one compact and simple design to reduce the devices and chip area significantly, compared to two separate voltage references in a conventional design. Fabricated in a 0.18- ${\mu }\text{m}$ CMOS process, the proposed CMOS voltage reference can provide two references of 331.8 and 660.3 mV with variation coefficients of 0.53% and 0.42%, respectively. The average TCs of $\text{V}_{\mathrm{ REF1}}$ and $\text{V}_{\mathrm{ REF2}}$ for a temperature range of −40 to 125°C are measured as 41.7 and 24.5 ppm/°C, respectively. The line sensitivity (LS) of $\text{V}_{\mathrm{ REF1}}$ is 0.0505 %/V with 0.6-1.8 V supply, and the LS of $\text{V}_{\mathrm{ REF2}}$ is 0.114 %/V with 0.8-1.8 V supply. The measured results show a competitive power supply ripple rejection, and the power consumption is only 4.12 nW with 0.8-V minimum supply at 25°C, while the active area is 0.0108 mm2.

Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

A −80 dB PSRR 4.99 ​ppm/°C TC bandgap reference with nonlinear compensation

A precision bandgap reference (BGR) with high power supply ripple rejection (PSRR) and low temperature coefficient (TC) is proposed for the peripheral compensation circuitry of active-matrix organic light-emitting diode (AMOLED) displays. The PSRR is enhanced by a coupling structure of the power supply and a feedback loop of the start-up circuit. Furthermore, a high-order nonlinear compensation method is proposed to reduce the temperature coefficient by utilizing the systematic nonlinear offset voltage within the bandgap circuit. Measurement results of the proposed BGR implemented in an industrial 0.25-μm CMOS process demonstrate a TC of 4.99 ​ppm/°C in a wide temperature range of −40 ​°C–130 ​°C. A PSRR around −80 dB is also achieved by the proposed circuit at low frequency.

A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit

This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ( $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ ) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz.

A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

A 0.6-V Minimum-Supply, 23.5 ppm/°C Subthreshold CMOS Voltage Reference With 0.45% Variation Coefficient

In this brief, a low-voltage low-temperature- coefficient (TC) subthreshold CMOS voltage reference (CVR) is presented. The proposed CVR employs the ${\Delta }\text{V}_{\mathbf{GS}}$ of different-threshold and same-threshold nMOS transistor pairs to generate the complementary-to-absolute-temperature and proportional-to-absolute-temperature voltages, respectively. Low TC with small variations and high power supply ripple rejection (PSRR) are achieved. The proposed design is fabricated in a standard 0.18- $ {\mu }\text{m}$ CMOS process. It measures an average reference voltage of 218.3 mV with a deviation of 0.97 mV and variation coefficient of 0.45%. It achieves an average TC of 23.5 ppm/°C for a temperature range of −40 °C to 125 °C. The measured PSRR is −66.4 dB, −42.4 dB and −42.3 dB at 10 Hz, 1 kHz and 10 MHz, respectively. The measured line sensitivity is 0.40%/V for 0.6 V to 2.0 V supply. The consumed power is 30.5 nW at 0.6-V supply.

A 0.4-V Wide Temperature Range All-MOSFET Subthreshold Voltage Reference With 0.027%/V Line Sensitivity

This brief presents a CMOS voltage reference for ultra-low-power applications, such as in implementable medical devices and energy harvesting-based wireless sensor nodes. In these applications, excellent capabilities to reject interference from power sources and work in low voltage to extend survival periods are critical for the voltage references. A transistor size-ratio determined current generator with high process and voltage independence is implemented by two same-threshold-voltage NMOS transistors, hence obtaining the precise reference voltage with an active load. The proposed circuit is fabricated in a standard 0.18- ${\mu }\text{m}$ CMOS process. Measurement results show that the prototype design provides a 210-mV reference with only 0.027% line sensitivity with a supply voltage from 1.8 V down to 0.4 V. The power supply ripple rejection at 10 Hz, 1 KHz, and 1 MHz is −59, 47, and 53 dB, respectively. The temperature coefficient is 82 ppm/°C in the temperature range from −40°C to +140 °C. Furthermore, the power consumption is only 9.6 nW at room temperature and the active area is 0.021 mm2.

Analysis and design of a current-mode bandgap reference with high power supply ripple rejection

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying a conventional frequency compensation scheme, the PSRR of the BGR is significantly enhanced. PSRRs of the BGR with the two different compensation techniques have been formulated and verified. Moreover, design considerations are presented, taking into account the critical parasitic capacitor's effect in PSRR. To our knowledge, this is the first time in the literature of explicitly demonstrating how the PSRR of a BGR is improved due to the frequency compensation. The feedback loop stability is also analyzed. The measured PSRR of an example BGR using the modified compensation fabricated in a standard 0.18-μm CMOS process is −77dB and −62dB at 1kHz, and 100kHz, respectively, with more than 40dB improvement at the high frequency ranges over the design with the classical compensation.

An amplifier‐offset‐insensitive and high PSRR subthreshold CMOS voltage reference

SummaryAn amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed CVR circuit can suppress the direct current offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions and improving the PSRR are presented. The proposed CVR circuit is implemented in a standard 0.18 μm complementary MOS process. Measured results show that the reference can run with down‐to 0.9 V supply voltage, while the power consumption is only 70 nW. The measured PSRR is better than −37 dB over the full frequency range.

A $5.2~\mu \text{A}$ Quiescent Current LDO Regulator With High Stability and Wide Load Range for CZT Detectors

Cadmium zinc telluride detectors are the highly considered for room-temperature hard X-ray and gamma-ray detection. The readout systems are needed in the detectors to output the detecting data. The features of power supplies are very important for the readout circuits. In this paper, a low-dropout (LDO) regulator with very low power consumption and wide load variation is presented. A combining compensation method which includes partially controlled load-tracking technique and equivalent series resistance compensation technique are proposed to enhance the loop stability of the LDO regulator. Meanwhile, high dc gain is obtained to improve the power supply ripple rejection (PSRR), which can decrease the noise from the power supply. The prototype LDO chip has been fabricated and tested with a standard 0.18- $\mu \text{m}$ CMOS technology. The measured results show that the LDO regulator can provide up to 150 mA load current with a stable output voltage of 2.8 V under an input voltage scope from 2.9 to 3.6 V. The measured PSRR is up to −60 dB. The output noise spectral densities are 1.16 $\mu \text{V}_{\mathrm {RMS}}/\sqrt {\mathrm {Hz}} $ and 211 nVRMS/s $\sqrt {\mathrm {Hz}} $ at 1 and 100 kHz, respectively, at load current of 150 mA. Especially, the ultralow quiescent currents of $5.2~\mu \text{A}$ at no load and $18.2~\mu \text{A}$ at full load bring great benefit to the ultralow power integrated readout systems.

A sub-1V 78-nA bandgap reference with curvature compensation

This paper presents a low power bandgap reference (BGR) with 573mV average output voltage and 0.95-V minimum supply voltage. Here, the resistor ratio of two types of resistors that have opposite temperature coefficient (TC) realizes a second-order curvature compensation. In addition, to reduce the supply voltage we adopt a voltage divider, and we also employ proportional to absolute temperature (PTAT) voltage generators to reduce the resistor values for low power applications. The proposed BGR fabricated in 65-nm CMOS achieves an average TC of 57ppm/°C from 0 to 100°C with 8 samples. The power dissipation at room temperature is 78nA and the power supply ripple rejection (PSRR) is −67dB at DC with 1.2V supply.

IC Design of the Band-Gap Reference and the Triangular Waveform Generator of Class D Audio Amplifier

Class D audio amplifier can extend battery life for its small cubage and high efficiency. In connection with the advantages of Class D audio amplifier, a class D audio amplifier with high efficiency and low distortion is designed in this paper. A negative feedback is established to improve the linearity of the amplifier and power supply ripple rejection ratio. Minimizing the distortion of the system requires high-speed sampling. High-speed comparator is designed to meet this requirement. Moreover, the work requires that the chip has a band-gap reference with low temperature coefficient and high power supply rejection ratio.

A new PWM controller with one-cycle response

This paper proposes a new nonlinear control technique that has one-cycle response, does not need a resetable integrator in the control path, and has nearly constant switching frequency. It obtains one-cycle response by forcing the error between the switched variable and the control reference to zero each cycle, while the on and off pulses of the controller are adjusted each cycle to ensure near constant switching frequency. The small switching frequency variation due to changes in the reference signal and supply voltage and delays in the circuit are quantified. Using double-edge modulation, the switching frequency variation is further reduced, thus, the associated signal distortion is minimized. An experimental 0-20 kHz bandwidth 95 W RMS power audio amplifier using the control method demonstrates the applicability of this control technique for high-fidelity audio applications. The amplifier has a power supply ripple rejection (PSRR) of 63 dB at 120 Hz. Additionally, the total harmonic distortion plus noise (THD+N) is less than 0.07% measured with a power supply ripple of 15%.