Power-on Reset Research Articles

A Robust Low‐Power Power‐On‐Reset Circuit With Dual Threshold Method

ABSTRACTIn this paper, a robust low‐power power‐on‐reset (POR) circuit with dual threshold method is proposed. The current‐based circuit exhibits good robustness with respect to process, voltage, temperature, and supply ramp variations. In contrast to conventional delay‐based pulse generation approaches, a dual threshold method is introduced to generate POR and brown‐out‐reset (BOR) pulse signals, resulting in ultralow quiescent current and a compact area. Implemented in the 55‐nm CMOS process, the proposed circuit achieves an accurate trigger‐point voltage with a temperature coefficient of 90.4 ppm/°C and a deviation to the ramp time of 2.9% for a range from 100 μs to 1 s. Furthermore, the quiescent current and active area are 0.3 nA and 4834 μm2, respectively, making it particularly suitable for energy harvesting systems.

An ultra-low quiescent current power-on reset circuit with DDPG method

An ultra-low quiescent current power-on reset (POR) circuit with double-delay pulse generation (DDPG) method is presented in this paper. The circuit is designed for non-volatile memory (NVM) systems, aiming to ensure reliable initialization and enhance overall efficiency. To address the challenge of inaccurate trigger-point voltage caused by process, voltage, temperature (PVT) and ramp time variations, a novel pulse generation method is proposed. Additionally, the circuit further improves the reliability of pulse duration through the utilization of low-cost current reference generators. Implemented in standard 40 nm CMOS technology, the delay-based POR circuit consumes only 0.24 nA quiescent current and occupies a compact area of 25.6μm×102μm. The simulation results demonstrate a typical pulse duration time of 28μs, with a temperature coefficient (TC) of 101.4 ppm/°C. The high reliability and low overhead of this circuit make it suitable for NVM systems and other fast power-on applications.

A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control

This article presents a highly efficient buck converter with sub-nW quiescent power and wide dynamic range for ultra-low-power (ULP) Internet-of-Things (IoT) systems-on-chip (SoCs). To optimize the SoC power consumption and performance, this buck converter supports fast dynamic voltage and frequency scaling (DVFS) and fast load-transient response (FLTR) using an asynchronous control scheme. To achieve robust and high-efficiency power delivery over process, voltage, and temperature variations, an adaptive deadtime controller (ADTC) is proposed with minimized area and power overhead. The power stage and gate drivers are optimized by a length split technique and a strong-up weak-down (SuWd) scheme to achieve low quiescent power. In addition, the buck converter is fully self-contained with a bias generator (BG), clock, and power-on-reset (PoR) integrated on-chip. Fabricated in 65-nm CMOS, measurement results show that the buck converter achieves 802-pW quiescent power and 93% peak efficiency at 1.5-V input voltage. The measured dynamic range is from 0.5 to 2.75 mW, which is over six orders of magnitude. The measured voltage droop is 56 mV for a 45-nA-to-1-mA load current step and DVFS up- and down-tracking takes 10.57 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.81~\mu \text{s}$ </tex-math></inline-formula> for an 88- and 92-mV reference step, respectively. This sub-nW buck converter integrates fast DVFS and FLTR features with a wide dynamic range making it suitable for ULP IoT applications.

Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin. Because this retention time is over 64,000 times longer than the JEDEC retention-time specification of 0.064 seconds, the DRAM refresh power can be reduced to a negligible level at the data center. To achieve this, the DRAM controller was modified to find weak rows by using three different data patterns at power-on reset and a reserved row of DRAM is used when access to a weak row address occurs during the normal operation.

A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> from a 1-V supply. The 2.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> XO features a low-frequency inaccuracy of 4 ppm/V. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation.

Safety of magnetic resonance imaging in patients with cardiac implantable electronic devices with generator and lead(s) brand mismatch.

Magnetic resonance imaging (MRI) is a valuable imaging modality for the assessment of both cardiac and non‐cardiac structures. With a growing population of patients with cardiovascular implantable electronic devices (CIEDs), 50%–75% of these patients will need an MRI. MRI‐conditional CIEDs have demonstrated safety of MRI scanning with such devices, yet non‐conditional devices such as hybrid CIEDs which have generator and lead brand mismatch may pose a safety risk. In this retrospective study, we examined the outcomes of patients with hybrid CIEDs undergoing MRI compared to those patients with non‐hybrid CIEDs. A total of 349 patients were included, of which 24 patients (7%) had hybrid CIEDs. The primary endpoint was the safety of MRI for patients with hybrid CIEDs as compared to those with non‐hybrid devices, measured by the rate of adverse events, including death, lead or generator failure needing immediate replacement, loss of capture, new onset arrhythmia, or power‐on reset. Secondary endpoints consisted of pre‐ and post‐MRI changes of decreased P‐wave or R‐wave sensing by ≥50%, changes in pacing lead impedance by ≥50 ohms, increase in pacing thresholds by ≥ 0.5 V at 0.4 ms, and decreasing battery voltage of ≥ 0.04 V. The primary endpoint of any adverse reaction was present in 1 (4.2%) patient with a hybrid device, and consistent of atrial tachyarrhythmia, and in 10 (3.1%) patients with a non‐hybrid device, and consisted of self‐limited atrial and non‐sustained ventricular arrhythmias; this was not statistically significant. No significant differences were found in the secondary endpoints. This study demonstrates that MRI in patients with hybrid CIEDs does not result in increased patient risk or significant device changes when compared to those patients who underwent MRI with non‐hybrid CIEDs.

W48. EFFICIENT HIPSC BASED DISEASE MODELLING USING CRISPR/CAS9

Experiments in high energy physics (HEP) operate at the forefront of detector technology, electronics, data acquisition (DAQ), data analysis, and computing. With the advent of high-energy accelerators running at large beam intensities, there is a great demand for radiation-hard high speed protocol for data transmission. Along with the detector data, communication signals like trigger, timing and control (TTC) information plays an important role. The TTC information needs to be transmitted over long distances using asynchronous communication links, which act as a bridge between the front-end radiation hard electronics and the DAQ. Maintaining the timing relationships and synchronization among payloads is an essential pre-requisite for the integrity of the acquired data. However, the phase relationship among the transmitted TTC signals gets disrupted due to the various sources of inter-signal interferences and channel link uncertainties. To address this challenge we have developed a phase alignment logic that can be applied over any asynchronous data-transmission protocol. We have implemented the proposed logic on the widely used radiation tolerant data-transmission protocol, called Gigabit Transceiver (GBT). The DAQ architecture needs to be resilient enough to avoid the loss of data or the errors in physics payload. The principal idea for implementation of the logic is to have an effective strategy to realign the synchronization without the need for power-on reset (PoR). The approach reduces the number of dead cycles that otherwise would have been utilized to minimize the timing errors. The chosen hardware for the experimental setup is 28 nm Stratix-V FPGA from Intel Inc. The benchmark of the system performance is illustrated in terms of the measurements of resource utilization, results of signal integrity, route delays, eye diagram and jitter analysis.

A Fully Integrated AC-DC Converter in 1 V CMOS for Electrostatic Vibration Energy Transducer with an Open Circuit Voltage of 10 V

This paper proposes an AC-DC converter for electrostatic vibration energy harvesting. The converter is composed of a CMOS full bridge rectifier and a CMOS shunt regulator. Even with 1 V CMOS, the open circuit voltage of the energy transducer can be as high as 10 V and beyond. Bandgap reference (BGR) inputs a regulated voltage, which is controlled by the output voltage of the BGR. Built-in power-on reset is introduced, which can minimize the silicon area and power to function normally found upon start-up. The AC-DC converter was fabricated with a 65 nm low-Vt 1 V CMOS with 0.081 mm2. 1 V regulation was measured successfully at 20–70 °C with a power conversion efficiency of 43%.

전자시스템의 파워 온 리셋 회로 설계

최근 고집적, 고기능화되어가고 있는 전자시스템의 초기 상태 안정화를 위해 파워 온 리셋 회로를 설계하였다. 파워 온 리셋 회로는 저항값이 비슷한 PMOS와 NMOS의 저항 비를 적용하여 구성하였다. 전원 전압의 상승시간과 관계없이 수십㎳ 이상의 충분한 리셋 시간을 확보하였고 전원 전압 상승시간이 200㎳일 때, 검출된 리셋 회로의 출력 피크 전압이 기존 회로보다 높은 전압에서 검출되어 보다 안정적인 리셋 동작을 수행 할 수 있다.

Operation and Control of 3-Phase Induction Motor using STM-32 Controller

Various automation processes are changing scenarios of controlling AC induction motors using AC drives. A robust system for switching on/off, varying the speed and direction of rotation of an industrial 3 Phase Induction Motor using VFD. Minimum variation in motor operation when it is running in loading condition. The STM32 is an optimal choice to support many applications with the same platform. The total pin-to-pin, peripheral, and software compatibility across the family gives you full flexibility across many devices. STM32 controller address three main energy requirements, High dynamic power efficiency in running mode, extremely low power when the application is on standby, and low voltage capability for direct battery operation. Built-in supervision in STM32 controller reduces the external components like power-on reset and watchdog timer with the independent clock. In this paper 3-phase induction, the motor operation is performed in real-time, and the difference between the given speed and actual speed is observed. To enhance the accuracy of the induction motor speed external VFD is placed between the power supply and motor which gives regulated output by varying 0-10V DC analog voltage as controlling input. It is a cost-effective solution to use a single controller than PLC.

Development of FPGA based phase alignment logic for the high speed protocol in HEP Experiments

Experiments in high energy physics (HEP) operate at the forefront of detector technology, electronics, data acquisition (DAQ), data analysis, and computing. With the advent of high-energy accelerators running at large beam intensities, there is a great demand for radiation-hard high speed protocol for data transmission. Along with the detector data, communication signals like trigger, timing and control (TTC) information plays an important role. The TTC information needs to be transmitted over long distances using asynchronous communication links, which act as a bridge between the front-end radiation hard electronics and the DAQ. Maintaining the timing relationships and synchronization among payloads is an essential pre-requisite for the integrity of the acquired data. However, the phase relationship among the transmitted TTC signals gets disrupted due to the various sources of inter-signal interferences and channel link uncertainties. To address this challenge we have developed a phase alignment logic that can be applied over any asynchronous data-transmission protocol. We have implemented the proposed logic on the widely used radiation tolerant data-transmission protocol, called Gigabit Transceiver (GBT). The DAQ architecture needs to be resilient enough to avoid the loss of data or the errors in physics payload. The principal idea for implementation of the logic is to have an effective strategy to realign the synchronization without the need for power-on reset (PoR). The approach reduces the number of dead cycles that otherwise would have been utilized to minimize the timing errors. The chosen hardware for the experimental setup is 28 nm Stratix-V FPGA from Intel Inc. The benchmark of the system performance is illustrated in terms of the measurements of resource utilization, results of signal integrity, route delays, eye diagram and jitter analysis.

Power Management IC With a Three-Phase Cold Self-Start for Thermoelectric Generators

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and 1080 μW output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV.

A nano-watt power-on reset circuit with Brown-Out detection capability

Ultra-low-power microcontrollers play an important role in system applications. In this paper, a Nano-watt Power-On Reset (POR) circuit with Brown-Out Detection (BOD) capability was proposed. The proposed circuit implemented in a 0.18 ​μm CMOS process, which contains long-reset and fast-reset time mode and provides a reset signal with approximately 3.314s and 22 ​ms, respectively. The embedded brown-out detection circuit can detect the event in time, as long as the abnormal supply voltage decreases to 1.4 ​V and the brown-out duration is longer than the microsecond range under 1.8 ​V–3.3 ​V. To further reduce power consumption, a bias state switching circuit and a Vpulse control signal generating circuit are proposed to reduce the static current in the start-up circuit and Schmitt triggers circuit. The circuit consumes less than 100 ​nA under 1.8 ​V–3.3 ​V power supply and occupies 110 ​× ​100 ​μm2 area.

Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms.

An Ultra-Low Quiescent Current Resistor-Less Power on Reset Circuit

An ultra-low quiescent current resistor-less power on reset circuit is presented in this brief. The circuit is used in energy harvesting systems to change boost converter from startup state to PWM modulation state. It integrates power on reset (POR) and brown out detection (BOD) functions without resistors or bandgaps overhead. Dual threshold detection (DTD) technology is used instead of a large size delay cell in generation of pulse signals. The circuit has been implemented in a 0.13μm standard CMOS technology. The active area and the quiescent current of the circuit are 154.4μm x 26.8μm and about 1nA, respectively. Ultra-low quiescent current and small area make the proposed circuit suitable to be applied in low power applications like energy harvesting and beyond.

A novel power-on-reset circuit for passive UHF RFID tag chip * * Project supported by the Key Laboratory of Agricultural Informatization Standardization, Ministry of Agriculture and Rural Affairs.

A novel power-on-reset (POR) circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of reset pulse for passive UHF RFID tags is presented in this paper. A proposed delay element was adopted for the features of small capacitances and wide power supply rise time range. An inverter was used as a two-inputs logic device to simplify the architecture of the circuit. The technology used for design and simulation is SMIC 0.18 μm RF. Simulation results show that the circuit functions well under different process corners with different power supply rise time, and is able to generate a POR signal after the power supply is briefly powered off. The static power consumption is less than 30 pA. Moreover, the circuit operates properly along with other modules of analog front-end.

Surge protection design with surge-to-digital converter for microelectronic circuits and systems

A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of VDD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.

Thoracic versus nonthoracic MR imaging for patients with an MR nonconditional cardiac implantable electronic device.

Observational studies have explored the safety of magnetic resonance (MR) scanning of patients with cardiac implantable electronic devices (CIEDs) that are not Food and Drug Administration approved for MR scanning ("nonconditional"). However, concern has been raised that MR scanning that includes the thoracic region may pose a higher risk. This study examines the safety of MR scanning of thoracic versus nonthoracic regions of patients with CIEDs. Patients underwent MR scanning utilizing an institutional protocol. CIED variables examined included sensing value, pacing capture threshold, lead impedance, and battery voltage. Regression analysis of the CIED variable differences (pre- to immediately post-MR and pre-MR to long-term follow-up) was performed to determine if CIED variable differences were dependent on region scanned (thoracic vs nonthoracic), time from CIED implant to MR scanning, or CIED type (pacemaker vs implantable cardioverter defibrillator). 238 patients (38% female, age 65 ± 15 years) underwent 339 MR scans, including 99 MR scans of the thoracic region. CIED variable differences to immediately post-MR or to long-term follow-up were not significantly different from zero (P>0.05) and there was no dependence upon region scanned (thoracic vs nonthoracic), time from CIED implant to MR scan, or CIED type. One power-on reset occurred in a patient that underwent a cardiac MR and the CIED was successfully reprogrammed. There were no clinical adverse effects. CIED variable differences following MR scan were not dependent on the region scanned (thoracic vs nonthoracic) and there were no clinical adverse effects in this prospective cohort.

Implanted Spinal Cord Stimulator Dysfunction After Electrical Shock

Spinal cord stimulation (SCS) has played a significant role in chronic pain since its inception during the late 1960s. There are several proposed mechanisms for SCS, one of which works via electrical pulses that target the dorsal horn of the spinal cord to inhibit afferent pain signals to achieve analgesia (Gate Control Theory). This can lead to an overall improvement in pain control when pharmacologic therapy is inadequate or ineffective. SCS also reduces pharmacologic needs, and hence alleviates side effects associated with opioids and other medications. We present the case of a 44-year-old male with chronic pain and an implanted SCS in place who presented to our university institution pain clinic for lumbar back pain with bilateral radiculopathy. He had suffered from back pain since 1996 and an implanted SCS was placed in June 2013. Three years after the SCS placement, the patient suffered an alternating (60 Hz) current 120-volt electrical shock while working on kitchen appliances resulting in SCS dysfunction. Prior to the electrocution event, the SCS was operating normally with a battery life registering three-fourths full. The stimulator was turned on one day prior to the incident. At the time of the electrical shock, the SCS was not actively stimulating. Following the incident, the patient tried to turn on the stimulator without success. Implantable devices, including pacemakers and neuromodulators, have a circuit protective mode which should prevent this type of occurrence. Using the physician programmer, we were unable to detect, connect, or interrogate his stimulator. With the help of a device representative, we attempted a physician mode recharge (PMR) for 10 minutes while in office. We were then able to pair the patient’s charger with the stimulator, and enter into the normal feedback-enabled charge mode. His charger display screen indicated a drained battery. After approximately 25 minutes of recharging, a second attempt to interrogate the device was successful. We hope this encourages all current and future SCS manufacturers to perform further device testing, quality control development, and research and development to make subsequent SCS even more reliable and resistant to damage or premature failure. Key words: Spinal cord stimulator (SCS), spinal cord generator, power-on reset (POR), SCS malfunction, electrical shock, dysfunction

Magnetic Resonance Imaging in Nondependent Pacemaker Patients with Pacemakers and Defibrillators with a Nearly Depleted Battery.

Magnetic resonance imaging (MRI) in patients with non-MRI-conditional cardiac implantable electronic devices (CIEDs) has been shown to be safe when performed under closely monitored protocols. However, the safety of MRI in patients with devices with a nearly depleted battery has not been reported. Prospective data were collected between January 2008 and May 2015 in patients with non-MRI-conditional CIEDs undergoing clinically indicated MRI under institutional protocol. Patients who were pacemaker dependent were excluded. Patients whose devices were at elective replacement indicator (ERI) at the time of MRI or close to ERI (ERI or replacement for battery depletion within 3 months of scan) were identified through database review and analyzed for clinical events. MRI scans (n = 569) were performed in 442 patients. Of these, we identified 13 scans performed with a nearly depleted battery in nine patients. All scans with implantable cardioverter defibrillators (ICDs, n = 9) were uneventful. However, two scans with pacemakers close to ERI resulted in a power-on-reset (PoR) event. One scan with a pacemaker close to ERI that was programmed to DOO mode reached ERI during MRI and automatically changed to VVI mode. Additionally, one scan with a pacemaker at ERI did not allow programming. All pacemakers with events were implanted before 2005. Patients with pacemakers and ICDs with a nearly depleted battery can safely undergo MRI when patients are not pacemaker dependent. Attention should be paid because old devices can result in PoR or ERI during MRI, which may lead to oversensing and inhibition of pacing.