Power MOSFET Research Articles

A novel MOSFET with lateral–vertical charge coupling for extremely low C gd

A novel MOSFET with lateral–vertical charge coupling (LVCC-MOSFET) is proposed in this paper. Lateral charge coupling is enabled by a metal field plate, lightly doped drain and P-Epi layer to reduce the C gd. Vertical charge coupling is enabled by a shield gate, sinker and P-Epi layer to support a high breakdown voltage (BV) and further reduce the C gd. By combining both lateral charge coupling and vertical charge coupling, which is first proposed in low-voltage power MOSFETs, the trade-off relationship between BV, R on and C gd can be significantly improved. It is verified by both small-signal analysis and transient capacitance simulation that the gate-to-drain capacitance of the proposed LVCC-MOSFET can be reduced by more than 99% without deterioration of BV and R on. The LVCC-MOSFET achieves 93.7% reduction in Q gd, and R on × Q gd is only 0.81 mΩ·nC, which is reduced by 93.9%. Furthermore, E on and E off can be reduced by 73.6% and 53.8%, respectively. The hot carrier injection reliability can be enhanced by reducing the electric field and the impact ionization generation rate near the drain-side gate oxide. Moreover, the LVCC-MOSFET can be feasibly manufactured with compatible fabrication process flow, and only three extra steps are needed.

The correlation of the drain-source capacitance variation and the P-pillar structures in a 4H-SiC quasi super junction MOSFET

In order to improve the trade-off between the 4H-SiC planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and super junction MOSFET (SJ-MOSFET), particularly on the drain to source capacitance (Cds) which affects the switching performance, this study investigates the Cds of the quasi SJ-MOSFETs with various P-pillar widths, depths, and concentrations. The measured results show (1) when the N-type region between the P-pillars (Epi-1 region) is fully depleted, the Cds value abruptly drops, (2) when the N-type drift region beneath the P-pillar (Epi-2 region) is fully depleted, the slope of the Cds-Vds curve slowly changes because of the small extension of the depletion region in the P-type region. This is because the wider P-pillar width will increase the magnitude of the abrupt drop of the Cds and make the drop occur earlier; the abrupt drop of the Cds will occur later and the magnitude increases when the P-pillar depth is deeper due to the larger P-type region; Moreover, increasing the P-pillar concentration not only initiates the abrupt drop earlier and increases the magnitude, but also increases the minimum saturation value of the Cds at a higher reverse bias. This study also reveals that the mechanism of the Cds formation in a quasi SJ-MOSFET is different from the planar MOSFET and SJ-MOSFET. Finally, the simulated results are used to validate the influence of the P-pillar structures on the Cds – Vds curves in a quasi SJ-MOSFET.

Origin and Recovery of Negative VTH Shift on 4H–SiC MOS Capacitors: An Analysis Based on Inverse Laplace Transform and Temperature-Dependent Measurements

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress.We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed.Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

Design strategy and working principle of GaN vertical trench gate MOSFETs with p-type shielding rings

Shielding ring (SR) structures are widely employed beneath the gate trench of vertical trench gate MOSFETs for the purpose of enhancing the gate oxide reliability and avoiding premature breakdown. To facilitate an in-depth understanding of the vertical power MOSFETs with p-type SRs (SR-MOSFETs), we numerically investigated the influence of the key parameters on the static characteristics of GaN-based vertical power SR-MOSFETs by TCAD simulation. We comprehensively elucidated the reach-through and non-reach through behaviors in the SR structures with different thicknesses, widths, and p-doping concentrations. We also illustrated the quasi-saturation effect by analyzing the 2D electron distribution and current density at the pinch-off point. With the same off-state voltage levels as conventional vertical MOSFETs, the SR-MOSFETs feature reduced on-state resistance and improved switching performance, which can provide theoretical guidance towards the development of high performance vertical gallium nitride power MOSFETs.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

A Drain Current Extraction Technique Using Source Parasitic Resistance and Inductance in SiC Power MOSFETs

A Drain Current Extraction Technique Using Source Parasitic Resistance and Inductance in SiC Power MOSFETs

A Split-Gate Power MOSFET Obtaining Ultra-Wide SOA Based on Time-Shared and Partitioned Conduction Gate Control

A Split-Gate Power MOSFET Obtaining Ultra-Wide SOA Based on Time-Shared and Partitioned Conduction Gate Control

Impact of SiC power MOSFET interface trap charges on UIS reliability under single pulse

In this paper, the unclamped inductive switching experimental results of a 1.2-kV rated N-Channel conventional power metal-oxide-semiconductor field-effect transistors are presented. The experimental results show that the sample devices can avoid a drain leakage current degradation under the bias conditions of Vds = 1520 V and Iav < 20 A. Notably, a severe avalanche failure current degradation is related to interface fixed trap charges. On this basis, the unclamped inductive switching for the 1.2-KV rated MOSFET with different interface fixed trap charges are given. The simulation results show that interface fixed trap charges determine the avalanche drain current degradation degree, and TCAD simulation shows that the interface fixed trap charges make the channel easier to activate. Thus, improving interface fixed trap charges can significantly reduce the degradation of avalanche drain leakage current in devices and enhance their avalanche robustness.

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET.

This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (RON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV2/RON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-RON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results.

Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs

We investigated the effects of the column length and fabrication method of the superjunction (SJ) structure on the reverse recovery characteristics of 1.2 kV silicon carbide (SiC) SJ metal–oxide–semiconductor field-effect transistors (MOSFETs). The voltage slope (dV/dt) and reverse recovery current slope (dir/dt) values during the reverse recovery of the SJ-MOSFETs with the SJ structure formed by Aluminum (Al) ion implantation were comparable to the values of MOSFETs without SJ structure at room temperature (RT), but they increased markedly with temperature. This is caused by the reduced p-column carrier concentration at RT during short recovery transient time due to the deep hole trap (DI center) introduced by ion implantation. At 175 °C, a softer reverse recovery waveform was obtained by shortening the SJ columns. Besides, Al ion implanted SJ-MOSFETs exhibited a weaker current dependence of the reverse recovery charge Qrr at 175 °C indicating a lower carrier injection level compared to the SJ-MOSFETs with the SJ structure formed by trench formation and epitaxial growth. This is caused by the short carrier lifetime of the SJ columns due to the Al ion implantation defects. The short and Al ion implanted SJ columns are effective for soft reverse recovery characteristics in SiC-SJ-MOSFETs.

Thickness Effect of Copper Clips on Power Module Packaging Design

The superior switching performance of SiC MOSFETs compared to Si devices is limited by packaging-related issues. High electromagnetic parasitics which lead to high voltage overshoots, and higher power losses are the main challenges of high frequency operation. Hence, packaging design modification and optimisation are necessary to accommodate faster switching. Copper clips replacing the bonding wires show promising results in reducing stray inductances, while enhancing the current conduction and heat dissipation since the clip are in contact with a larger area of the semiconductor chip. Silver sintering instead of soldering further improves the electrothermal behaviour. This paper investigates numerically various thicknesses of the copper clips and their effect on double-sided silver sintering, half-bridge 1200V/400A SiC MOSFET power module. Moreover, the silver layer thickness is varied to reduce th maximum stresses on the chip - silver interface.

Modelling the 3-D Charge-Sharing in Field-Plate Power MOSFETs With Circular Layouts

Modelling the 3-D Charge-Sharing in Field-Plate Power MOSFETs With Circular Layouts

Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit.

Post-trench restoration for vertical GaN power devices

The impact of the post-trench restoration on the electrical characteristics of vertical GaN power devices is systematically investigated in this work. Following the achievement of microtrench-free GaN trench structure with modified dry etching conditions, the post-trench tetramethylammonium hydroxide (TMAH)-based wet etching and UV/Ozone-based oxidation process are employed to further refine the trench profile. It is shown that the c-plane trench bottom is restored to the level of unetched surface, as evidenced by the improved Schottky interface. Additionally, the post-trench treatment exhibits the anisotropic characteristics with the preferred rounded corner profile on m-plane sidewall compared to a-plane sidewall. The simulations and experimental results demonstrate that the trench MOS barrier Schottky (TMBS) rectifier based on m-plane sidewall could suppress the electric field crowding at the trench corner and, hence, reduce the reverse leakage current by 1–2 orders of magnitude. Furthermore, the MOSCAP test structures were fabricated on the trenches. The extracted interface trap density (Dit) confirms the effective restoration of trench bottom. However, the sidewall surface exhibits the relatively large Dit, which emphasizes the necessity of optimizing the sidewall, particularly for devices incorporating sidewall channel. The demonstrated post-trench restoration technique improves the surface quality and trench structure for the significantly enhanced electrical performances, which is essential for the development of vertical GaN power devices.

Combined Fabrication and Performance Evaluation of TOPCon Back‐Contact Solar Cells with Lateral Power Metal‐Oxide‐Semiconductor Field‐Effect Transistors on a Single Substrate

Nowadays, an increasing share of photovoltaic (PV) systems makes use of module‐ or submodule‐level power electronics (PE). Furthermore, PE is used in stand‐alone devices powered by PV‐storage solutions. One way to facilitate further implementation of PE in PV applications is to integrate PE components into crystalline silicon PV cells. Herein, the COSMOS device is introduced, denoting COmbined Solar cell and metal‐oxide‐semiconductor field‐effect transistor (MOSFET). Specifically, the combined manufacturing of lateral power MOSFETs and interdigitated back contact solar cells with tunnel‐oxide passivated contacts (TOPCon) on a single wafer is reported. Many steps of the proposed process flow are used for the fabrication of both devices, enabling cost‐effective integration of the MOSFET. Both n‐type solar cells with integrated p‐channel MOSFETs (PMOS) and p‐type solar cells with integrated n‐channel MOSFETs (NMOS) are successfully manufactured. NMOS devices perform better in achieving low on‐resistance, while PMOS devices exhibit lower leakage currents. Furthermore, the study reveals integration challenges where off‐state leakage currents of the MOSFET can increase due to illumination and specific configurations of monolithic interconnections between the MOSFET and the solar cell. Nevertheless, for both n‐type and p‐type solar cells, efficiencies exceeding 20% are achieved, highlighting the potential of the proposed process for COSMOS devices.

Demonstration of recycling process for GaN substrates using laser slicing technique towards cost reduction of GaN vertical power MOSFETs

Abstract To address the issue of the high cost of GaN substrates, a recycling process for GaN substrates using a laser slicing technique was investigated. The channel properties of lateral MOSFETs and the reverse characteristics of vertical PN diodes, which represent the main components of vertical power devices, exhibited no degradation either before and after laser slicing or due to the overall GaN substrate recycling process. This result indicates that the proposed recycling process is an effective method for reducing the cost of GaN substrates and has the potential to encourage the popularization of GaN vertical power devices.

An Investigation of Body Diode Reliability in Commercial 1.2 kV SiC Power MOSFETs with Planar and Trench Structures.

The body diode degradation in SiC power MOSFETs has been demonstrated to be caused by basal plane dislocation (BPD)-induced stacking faults (SFs) in the drift region. To enhance the reliability of the body diode, many process and structural improvements have been proposed to eliminate BPDs in the drift region, ensuring that commercial SiC wafers for 1.2 kV devices are of high quality. Thus, investigating the body diode reliability in commercial planar and trench SiC power MOSFETs made from SiC wafers with similar quality has attracted attention in the industry. In this work, current stress is applied on the body diodes of 1.2 kV commercial planar and trench SiC power MOSFETs under the off-state. The results show that the body diodes of planar and trench devices with a shallow P+ depth are highly reliable, while those of the trench devices with the deep P+ implantation exhibit significant degradation. In conclusion, the body diode degradation in trench devices is mainly influenced by P+ implantation-induced BPDs. Therefore, a trade-off design by controlling the implantation depth/dose and maximizing the device performance is crucial. Moreover, the deep JFET design is confirmed to further improve the body diode reliability in planar devices.

Evaluation of custom-designed lateral power transistors in a silicon-on-insulator process in a synchronous buck converter

Most of todays power converters are based on power semiconductors, which are built in vertical power semiconductor processes. These devices result in limited packaging possibilities, which lead to physically long galvanic connections and therefore high external electromagnetic fields. These fields compromise power quality significantly. Therefore this paper examines the possibility to use lateral silicon-on-insulator power MOSFETs and uses the custom-made devices in a 48 V to 12 V synchronous buck converter in continuous conduction mode. The converter is designed based on custom made power transistors, implemented and verified by experimental results. The resulting efficiency of the 1 Wconverter is around 93 % across a wide load range and its temperature rise is less the 10 C. This leads to the conclusion, that modern lateral silicon-on-insulator power processes allow high integration of power stages and therefore promise lower emissions, leading to higher power quality.

A High-Efficiency DC-DC Converter Based on Series/Parallel Switched Inductor Capacitors for Ultra-High Voltage Gains

A high-efficiency DC-DC converter employing a modified architecture called the hybrid switched inductor–capacitor series (MHSLCS) is proposed in this paper. The primary goal is to achieve a notably ultra-high voltage gain for renewable energy systems (RESs). Furthermore, the use of only one input capacitor in the MHSLCS eliminates pulsations in the input current at both low and high duty ratios. The proposed converter integrates the MHSLCS with a modified switched capacitor (MSC) that interleaves with the main MOSFET, effectively doubling the voltage transfer gain. Additionally, a modified hybrid switched inductor–capacitor parallel (MHSLCP) is incorporated in parallel with an interleaved auxiliary MOSFET. Both MOSFETs, combined with the MSC, contribute to achieving an ultra-high voltage gain. In addition, the inductors of the MHSLCP operate in a discontinuous conduction mode (DCM), which results in significant stress reductions in the power diodes and switches at high output voltages. The advantages of the proposed converter are multifaceted, demonstrating a high efficiency while minimizing the voltage in power device diodes and MOSFETs. The use of low inductance and capacitance values at high switching frequencies further enhances the performance. Wide-bandgap (WBG) power devices are employed to achieve the desired high voltage gain and efficiency. The proposed converter was designed with a PCB and underwent experimental testing to validate laboratory results. The proposed converter boosted the input voltage from 30 V to a variable output voltage between 325 V and 500 V, with a power output of 325 watts and an efficiency of 95.5%.

Health State Estimation of Power MOSFETs With Multistate Probability Prediction-Based Particle Filter

Health State Estimation of Power MOSFETs With Multistate Probability Prediction-Based Particle Filter