Power Minimization Techniques Research Articles

A Novel Test Pattern Optimization Method Using Recurrent Neural Network

Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS’89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage.

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits (ICs) fabrication industries. Because whenever device size comes down into narrow, designers facing many power density issues should be reduced by scaling threshold voltage and supply voltage. Initially, Complementary Metal Oxide Semiconductor (CMOS) technology supports power saving up to 32 nm gate length, but further scaling causes short severe channel effects such as threshold voltage swing, mobility degradation, and more leakage power (less than 32) at gate length. Hence, it directly affects the arithmetic logic unit (ALU), which suffers a significant power density of the scaled multi-core architecture. Therefore, it losses reliability features to get overheating and increased temperature. This paper presents a novel power minimization technique for active 4-bit ALU operations using Fin Field Effect Transistor (FinFET) at 22 nm technology. Based on this, a diode is directly connected to the load transistor, and it is active only at the saturation region as a function. Thereby, the access transistor can cutoff of the leakage current, and sleep transistors control the flow of leakage current corresponding to each instant ALU operation. The combination of transistors (access and sleep) reduces the leakage current from micro to nano-ampere. Further, the power minimization is achieved by connecting the number of transistors (6T and 10T) of the FinFET structure to ALU with 22 nm technology. For simulation concerns, a Tanner (T-Spice) with 22 nm technology implements the proposed design, which reduces threshold voltage swing, supply power, leakage current, gate length delay, etc. As a result, it is quite suitable for the ALU architecture of a high-speed multi-core processor.

Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits

Comparators play an important role in designing of SAR ADC. In this paper we achieve the required performance of SAR ADC at minimum power usage. Using of comparators will reduce the power and noise, Dynamic latch circuit used in comparator increases the speed. The differential amplifier is also discussed. Here we will get to know about Ramp ADC and also about various DAC’s like M-DAC and AUX-DAC. The time-interleaving technique is the design technique that is used to increase the speed.

New Power Minimization Techniques in Hybrid Distributed Antenna Systems With Orthogonal and Non-Orthogonal Multiple Access

Distributed antenna systems (DASs) have been proposed as a solution to supply the ever increasing capacity demands in next generation networks. This paper considers the power minimization problem in hybrid DAS where antennas are supplied by various-low power and high power-energy sources. Antenna-specific power limits are considered and the problem is reformulated in this new hybrid context. The optimal power allocation problem is first formulated and solved in the orthogonal multiplexing scenario. Different resource allocations schemes based on this optimal power allocation are then proposed for the orthogonal and non-orthogonal multiplexing contexts. Simulation results illustrate the efficiency of the proposed algorithms and show the importance of non-orthogonal multiplexing in the reduction of the total transmission power, especially in hybrid antenna systems.

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices

In present scenario, the portable wireless devices like mobile phones are used by almost every human being for communication purpose. Mobile devices are equipped with a processing element that is responsible for performing all the controlling and computational tasks. Most of the computational tasks inside the processing element are performed by ALU circuit. ALU is considered as the computational engine and responsible for high power consumption. Previously, microprocessors and microcontrollers were the choice of designers but nowadays the horizon has been shifted to FPGAs and SOCs as a processing element in mobile devices. Obviously, FPGAs have numerous advantages over processors and the growing need of applications compels the designers to use FPGAs for fast processing. Although FPGAs fulfils the requirement of designers but they suffer from the disadvantage of high power consumption due to their complex circuitry. The demand of high performance and low power devices creates a bottleneck in front of designers specifically for battery operated portable wireless devices. So, this paper presents some power minimization techniques that can be applied on communication centric designs targeted to FPGAs. There are different techniques given in the literature but most of them are applied at device level only. This paper gives an insight to minimize the power at architectural level of design hierarchy using XPower Analyzer as a CAD tool. The proposed techniques are applied on arithmetic and logical unit circuit for analysis purpose, as ALU is the heart of processing elements used in portable wireless devices. The circuit has been verified and realized on XILINX ISE directed to Spartan 3E XC3S250E FPGA. The analysis illustrates significant improvement in the power consumption.

Tutorial: Design and Optimization of Power Delivery Networks

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

Look up Table Based Low Power Analog Circuit Testing

In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the analog circuit, is designed and is taken for testing purpose. Fault coverage is identified after fault modeling, fault injection and fault simulation. More than 93% fault coverage is achieved and there is a scope of increasing more fault coverage. Since analog testing prefaces the challenge of power dissipation during testing, some power minimization techniques like sleepy stack method and current correlation method have adhered during the testing process. Test power reduction up to 84 % is achieved in this work.

Distributed Beamforming in Two-Way Relay Networks With Interference and Imperfect CSI

This paper studies the problem of optimal beamforming and power allocation for an amplify-and-forward (AF)-based two-way relaying network in the presence of interference and channel state information (CSI) uncertainty. In particular, we obtain the beamforming vector as well as the users’ transmit powers under two assumptions on the availability of the CSI of the interfering links, namely norm-bounded uncertainty model and the second-order statistics scenario. To do so, we develop two design approaches. The first approach is based on the total transmit power minimization technique. We start with the norm-bounded uncertainty model and derive the optimal solution to the corresponding problem. To reduce the computational complexity, we also develop a low-complexity algorithm which offers performance that is very close to the optimal one. In the second approach, we apply a signal-to-interference-plus-noise ratio (SINR) balancing technique. We propose another low-complexity algorithm based on the SINR balancing criteria. Next, we consider the scenario where the second-order statistics of the CSIs are available. Again we start with the total power minimization method and derive both optimal and suboptimal algorithms. Finally, we apply the SINR balancing technique to this scenario and develop another low-complexity algorithm, which is suitable for practice.

Comparison of Leakage Power Reduction Techniques in 65nm Technologies

The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper comparison of Leakage reduction technique is developed in Cadence Virtuoso in 65nm regime with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.

Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

Coupled switched capacitance causes crosstalk in ultra deep submicron/nanometer VLSI fabrication, which leads to power dissipation, delay faults, and logical malfunctions. We present the first memoryless transition bus-encoding technique for power minimization, error-correction, and elimination of crosstalk simultaneously. To accomplish this, we generalize balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. Optimal or asymptotically optimal constant weight codes eliminating each kind of crosstalk are constructed.

A Sat Based Scheduling Technique for Peak Power Minimization

Abstract With tremendous compaction in semiconductor devices over the past decades, power consumption in circuits has become an im- portant design concern. Peak power is the maximum instantaneous power at a particular time. For devices having multiple modes of operational unit, the highest power mode determines area, packaging and possibly heat sink cost of goods. In this paper, we present a technique for the minimization of peak power consumption in a design of circuit at the high-level synthesis stage. A PB-SAT based model has been proposed that minimizes the peak power and satisfies the resource constraints. Experimental results are obtained by applying the proposed method on high-level synthesis benchmark circuits for different resource constraints.

Leakage Power Reduction Using Sleepy StackPower Gating Technique

The project presents the power gating techniques used for leakage power reduction.The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper a novel Leakage reduction technique is developed in Tanner EDA tool.

Wake-up radio receiver based power minimization techniques for wireless sensor networks: A review

In a short period of time Wireless Sensor Networks (WSN) captured the imagination of many researchers with the number of applications growing rapidly. The applications span large domains including mobile digital health, structural and environmental monitoring, smart home, energy efficient buildings, agriculture, smart cities, etc. WSN are also an important contributor to the fast emerging Internet of Things infrastructure. Some of the design specifications for WSN include reliability, accuracy, cost, deployment versatility, power consumption, etc. Power consumption is (most often) the dominant constraint in designing such systems. This constraint has multi-dimensional implications such as battery type and size, energy harvester design, lifetime of the deployment, intelligent sensing capability, etc. Power optimization techniques have to explore a large design search space. Energy neutral system implementation is the ultimate goal in wireless sensor networks ensuring a perpetual/greener use and represents a hot topic of research. Several recent advances promise significant reduction of the overall sensor network power consumption. These advances include novel sensors and sensor interfaces, low energy wireless transceivers, low power processing, efficient energy harvesters, etc. This paper reviews a number of system level power management methodologies for Wireless Sensor Networks. Especially, the paper is focusing on the promising technology of nano-Watt wake-up radio receiver and its combination with mature power management techniques to achieve better performance. Some of the presented techniques are then applied in the context of low cost and battery powered toy robots.

Content-aware resource allocation in OFDM systems for energy-efficient video transmission

Demand on multimedia content by consumers' handheld devices over wireless channels is on the increase. In view of the accelerated trend towards consumption of high quality video, power utilization by mobile devices is expected to excessively increase. Hence, it becomes equally important to advance more efficient power minimization techniques, in light of the short battery life in portable devices. However, power minimization algorithms that adopt consumers' perceptual quality of video have not received adequate research. This paper proposes a joint optimization of energy and quality requirements in a multiuser orthogonal frequencydivision multiplexing environment. A multi-objective optimization problem is formulated with the aim to identify bitrate allocations among users such that total power is minimized, and average quality is maximized. For this, a content-aware and energy-efficient resource allocation scheme (CaERAS) is proposed based on genetic and greedy algorithms. Simulation results show that CaERAS, as a lowcomplexity scheme, outperforms comparable methods in terms of efficiency and selectivity of suboptimal solutions. It is shown to acquire a suboptimal solution in as low as 0.0025 of the search space in previous methods. Also, a significant average saving of 85.66% in required energy is observed in broadcast transmission as opposed to unicast transmission.

Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs

This paper proposes a novel fast and unified mixed-signal design methodology by incorporating manufacturing process variation awareness in power, performance, and parasitic optimization. The design of a process variation aware voltage controlled oscillator (VCO) at nano-CMOS technologies is demonstrated as a case study. Through accurate simulations it is shown that process variations have a drastic effect on performance metrics such as the center frequency of the VCO. In the presence of worst-case process variation, performance optimization of the VCO is applied, along with a dual-oxide technique for power minimization. The final product of the proposed process-variation aware methodology is an optimal physical design. The proposed methodology achieves 25% power reduction (including leakage) with only 1% degradation in center frequency compared to the target, in the presence of worst-case process variation and parasitics, with a 41% area penalty.

Clock-Gating Approach to Low Power Domino Circuit Synthesis

Domino logic is often the choice for designing high speed CMOS circuits. Switching of gates in such a CMOS circuit, account for much of its dynamic power dissipation. Power minimization techniques like clock-gating, energy recovery clock, power gating and so on have limitations namely penalty on clock delay, logic overhead, synchronization issues and so on. In this work, we propose a method for implementing clock-gating to a Domino logic-based circuit, using a pattern recognition approach. For a given Domino circuit, first we identify a list of favourable gate patterns (FGPs) that can undergo clock-gating. Next, based on a graph-matching algorithm, we map these FGPs to the circuit elements achieving savings in power and area. Finally, we find an optimum set of patterns so that maximum power savings can be obtained with a minimum penalty on area. We have tested the efficacy of our approach with a set of standard benchmark circuits. Our proposed clock-gating approach offered 15% improvement in power savings and 18% improvement in area penalty compared to the existing work.

Optimizing the Power Delivery Network in a Smartphone Platform

Smartphones consume a significant amount of power. Indeed, they can hardly provide a full day of use between charging operations even with a 2000 mAh battery. While power minimization and dynamic power management techniques have been heavily explored to improve the power efficiency of modules (processors, memory, display, GPS, etc.) inside a smartphone platform, there is one critical factor that is often overlooked: the power conversion efficiency of the power delivery network (PDN). This paper focuses on dc-dc converters, which play a pivotal role in the PDN of the smartphone platform. Starting from detailed models of the dc–dc converter designs, two optimization methods are presented: 1) static switch sizing to maximize the efficiency of a dc–dc converter under statistical loading profiles and 2) dynamic switch modulation to achieve the high efficiency enhancement under dynamically varying load conditions. To verify the efficacy of the optimization methods in actual smartphone platforms, this paper also presents a characterization procedure for the PDN. The procedure is as follows: 1) group the modules in the smartphone platform together and use profiling to estimate their average and peak power consumption levels and 2) build an equivalent dc–dc converter model for the power delivery path from the battery source to each group of modules and use linear regression to estimate the conversion efficiency of the corresponding equivalent converter. Experimental results demonstrate that the static switch sizing can achieve 6% power conversion efficiency enhancement, which translates to 19% reduction in power loss general usage of the smartphone. The dynamic switch modulation accomplishes similar improvement at the same condition, while also achieving high efficiency enhancement in various load conditions.

An Efficient Routing Protocol for Mobile Ad Hoc Network for Secured Communication and Minimized Power Consumption

Security and reliable communication is challenging task in mobile Ad Hoc network. Through mobility of network device compromised with attack and loss of data. For the prevention of attack and reliable communication,various authors proposed a method of sec ured routing protocol such as SAODV and SB RP (secured backup routing protocol). The process of these methods work along with route discovery and route maintains, discovery and route maintained needed more power consumption for that process. The power of devices is decrease during such process and network lifetimes expire.In this paper, we modified the secured stateless protocol for secured routing and minimized the utilization of power during path discovering and establishment. For the authentication of g roup node used group signature technique and sleep mode threshold concept for power minimization. Our proposed technique is si mulated in ns-2 and compare to other routing protocol gives a better performance in comparison toenergy consumption and throughput of network.

An Optimization Mechanism Intended for Static Power Reduction Using Dual‐VthTechnique

Power consumption reduction is a challenge nowadays. Techniques for dynamic and static power minimization have been proposed, but most of them are very time consuming. This work proposes an algorithm for reducing static power, which can be perfectly inserted in the conventional design flow for integrated systems considering an open source environment (open access infrastructure). The proposed approach, based on a Dual‐Threshold technique, replaces part of the cells of the circuit by cells with a higher threshold voltage without resulting in timing violations in the circuit. The decision to replace a cell is based on timing estimates of the circuit modeling with the cell replacement, before it is actually replaced. The fact that only some cells are replaced every iteration results in a reduction of the runtime of the algorithm. Additionally, results showed a reduction in static power up to 39.28%, when applying the proposed approach in the ISCAS85 benchmark circuits.

Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications

The leakage power dissipation has become one of the most challenging issues in low power VLSI circuit designs especially with on-chip devices as it doubles for every two years[4]-[5]. The scaling down of threshold voltage has contributed enormously towards increase in subthreshold leakage current thereby making the static (leakage) power dissipation very high. According to International Technology Roadmap for Semiconductors (ITRS), the total power dissipation may be significantly contributed by leakage power dissipation [1]. The battery operated devices with long duration in standby mode may be drained out very quickly due to the leakage power. In CMOS submicron technologies, leakage power dissipation plays a significant role. However, various low power design techniques for efficient minimization of leakage power are proposed in the literature review. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper. The present research study and its corresponding analysis are mainly focusing on circuit performance parameters. It is implied from the current literature that only an appropriate choice of leakage power minimization technique for a specific application can be effectively carried by a VLSI circuit designer based on sequential analytical approach.