A Sat Based Scheduling Technique for Peak Power Minimization

Abstract

Abstract With tremendous compaction in semiconductor devices over the past decades, power consumption in circuits has become an im- portant design concern. Peak power is the maximum instantaneous power at a particular time. For devices having multiple modes of operational unit, the highest power mode determines area, packaging and possibly heat sink cost of goods. In this paper, we present a technique for the minimization of peak power consumption in a design of circuit at the high-level synthesis stage. A PB-SAT based model has been proposed that minimizes the peak power and satisfies the resource constraints. Experimental results are obtained by applying the proposed method on high-level synthesis benchmark circuits for different resource constraints.