Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs

Abstract

This paper proposes a novel fast and unified mixed-signal design methodology by incorporating manufacturing process variation awareness in power, performance, and parasitic optimization. The design of a process variation aware voltage controlled oscillator (VCO) at nano-CMOS technologies is demonstrated as a case study. Through accurate simulations it is shown that process variations have a drastic effect on performance metrics such as the center frequency of the VCO. In the presence of worst-case process variation, performance optimization of the VCO is applied, along with a dual-oxide technique for power minimization. The final product of the proposed process-variation aware methodology is an optimal physical design. The proposed methodology achieves 25% power reduction (including leakage) with only 1% degradation in center frequency compared to the target, in the presence of worst-case process variation and parasitics, with a 41% area penalty.