Power Management IC Research Articles

A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes

A 0.25 cm 3 autonomous energy harvesting micro-platform is realized to efficiently scavenge, rectify and store ambient vibration energy with batteryless cold start-up and zero sleep-mode power consumption. The fabricated compact system integrates a high-performance vacuum-packaged piezoelectric MEMS energy harvester with a power management IC and surface-mount components including an ultra-capacitor. The power management circuit incorporates a rectification stage with ~30 mV voltage drop, a bias-flip stage with a novel control system for increased harvesting efficiency, a trickle charger for permanent storage of harvested energy, and a low power supply-independent bias circuitry. The overall system weighs less than 0.6 grams, does not require a pre-charged battery, and has power consumption of 0.5 µW in active-mode and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$&lt; $</tex></formula> 10 pW in sleep-mode operation. While excited with 1 g vibration, the platform is tested to charge an initially depleted 70 mF ultra-capacitor to 1.85 V in 50 minutes (at 155 Hz vibration), and a 20 mF ultra-capacitor to 1.35 V in 7.5 min (at 419 Hz). The end-to-end rectification efficiency from the harvester to the ultra-capacitor is measured as 58–86%. The system can harvest from a minimum vibration level of 0.1 g.

Pulsewidth modulated controller integrated circuit: Four decades of progress [A Look Back

The simple pulsewidth modulated (PWM) controller IC has made substantial progress in the last 39 years. Along the way, it has left several milestones. In addition, there is much more to achieve, especially as digital PWM controller chips begin to gain ground in the analog world. From a simple monolithic bipolar chip in 1975, designed by Silicon General‚s cofounder and power designer, Bob Mammano, to control a switched-mode power supply (SMPS), the pulsewidth modulated (PWM) controller architecture and integration has made remarkable progress in the last 39 years. Four decades later, advances in topology, semiconductor processes, and packaging have enabled this simple control circuit with a few functional blocks on a bipolar chip to reach everincreasing levels of integration, resulting in a complete power supply as a single board-mountable component. In addition to stimulating the development of SMPS supplies and creating a gigantic market for switching power supplies, it has also enabled a powermanagement integrated circuits (PMICs) industry that is worth tens of billions of dollars today. By research firm Micro-Tech Consultants' estimate, the switching power supply market comprising ac-dc switchers and dc-dc converters was worth over US$29 billion last year and is expected to increase to over US$29.5 billion this year.

다양한 부하조건에 호환 가능한 프로그래머블 스마트 충전기

A programmable smart charger compatible to various load conditions is proposed in this paper. Since the proposed smart charger is compatible to various mobile devices having different rated voltage and power, it is convenient for carrying and easy to standardize many kinds of battery chargers. Moreover, since it uses the input impedance and built-in PMIC (Power management IC) of the load system to recognize the connection state and specifications of load system, hardware changes of load system is not only hardly necessary but it also features no addition communication cable and easy implementation. To confirm the validity of the proposed charger, the theoretical analysis and experiment results from a prototype compatible to three load conditions 5V/1A, 5V/2A and 12V/1A are provided.

A Single-Inductor Eight-Channel Output DC–DC Converter With Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator

This paper describes a time-limited power distribution control technique that can be used for single-inductor multiple-output (SIMO) DC-DC converter with many unbalanced loads. Furthermore, the true all-comparator control technique that raises no stability or complexity issues is proposed. This all-comparator technique for SIMO converters is realized only with a single shared hysteresis comparator at a constant switching frequency of 800 kHz. This leads to the development of a new inductor peak-current control technique that does not require compensators and a phase-locked loop. This converter is analyzed and compared with existing SIMO converters with respect to the requirements of next-generation power management ICs. The maximum efficiency of the converter reaches 92%. The fabricated chip supporting eight-channel outputs is implemented in a 0.35-μm CMOS process and occupies an area of 2.4 × 2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

PwrSoC (integration of micro-magnetic inductors/transformers with active semiconductors) for more than Moore technologies

This paper introduces the concept of power supply on chip (PwrSoC) which will enable the development of next-generation, functionally integrated, power management platforms with applications in dc-dc conversion, gate drives, isolated power transmission and ultimately, high granularity, on-chip, power management for mixed-signal, SOC chips. PwrSoC will integrate power passives with the power management IC, in a 3D stacked or monolithic form factor, thereby delivering the performance of a high- efficiency dc-dc converter within the footprint of a low-efficiency linear regulator. A central element of the PwrSoC concept is the fabrication of power micro-magnetics on silicon to deliver micro-inductors and micro-transformers. The paper details the magnetics on silicon process which combines thin film magnetic core technology with electroplated copper conductors. Measured data for micro-inductors show inductance operation up to 20 MHz, footprints down to 0.5 mm 2 , efficiencies up to 93% and dc current carrying capability up to 600 mA. Measurements on micro-transformers show voltage gain of approximately - 1 dB at between 10 MHz and 30 MHz.

Reduction of Equivalent Series Inductor Effect in Delay-Ripple Reshaped Constant On-Time Control for Buck Converter With Multilayer Ceramic Capacitors

The stability of conventional constant on-time control buck converter is constrained by the time constant, which is the product of the output capacitor and its equivalent series resistance (ESR). Specialty polymer capacitor which is mostly used as output capacitor for such a consideration although it limits the performance of converter. On the other hand, the multilayer ceramic capacitors are widely used in commercial power management ICs due to the advantages of low cost and ESR. However, the stability often confronts with the subharmonic problem caused by small time constant. A differential-zero compensator with the noise margin enhancement (DZC-NME) technique in constant on-time control buck dc-dc converter with output ceramic capacitor is proposed in this paper. Thus, the proposed DZC-NME technique not only eliminates the limit of large time constant but also tolerates the existence of equivalent series inductor (ESL) effect. Experiment results demonstrate small output ripple of 10 mV and high efficiency of 91% when ESR is smaller than 1 mΩ and large interference from ESL effect is 40 mV.

A Wireless Magnetoresistive Sensing System for an Intraoral Tongue-Computer Interface

Tongue drive system (TDS) is a tongue-operated, minimally invasive, unobtrusive, and wireless assistive technology (AT) that infers users' intentions by detecting their voluntary tongue motion and translating them into user-defined commands. Here we present the new intraoral version of the TDS (iTDS), which has been implemented in the form of a dental retainer. The iTDS system-on-a-chip (SoC) features a configurable analog front-end (AFE) that reads the magnetic field variations inside the mouth from four 3-axial magnetoresistive sensors located at four corners of the iTDS printed circuit board (PCB). A dual-band transmitter (Tx) on the same chip operates at 27 and 432 MHz in the Industrial/Scientific/Medical (ISM) band to allow users to switch in the presence of external interference. The Tx streams the digitized samples to a custom-designed TDS universal interface, built from commercial off-the-shelf (COTS) components, which delivers the iTDS data to other devices such as smartphones, personal computers (PC), and powered wheelchairs (PWC). Another key block on the iTDS SoC is the power management integrated circuit (PMIC), which provides individually regulated and duty-cycled 1.8 V supplies for sensors, AFE, Tx, and digital control blocks. The PMIC also charges a 50 mAh Li-ion battery with constant current up to 4.2 V, and recovers data and clock to update its configuration register through a 13.56 MHz inductive link. The iTDS SoC has been implemented in a 0.5-μm standard CMOS process and consumes 3.7 mW on average.

Reliability LU Appropriate Designs in an HV nLDMOS

In an nLDMOS, both the drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic are presented in this work. In this paper, we will detailedly discuss the trigger voltage (Vt1) and holding voltage (Vh) distribution of a novel high-voltage (HV) nLDMOS device. It’s a novel method to reduce the Vt1 and to increase the Vh. Therefore, these efforts will be very suitable for the HV applications in power management ICs.

Design of 256 bit single-poly MTP memory based on BCD process

We propose a single-poly MTP (multi-time programmable) cell consisting of one capacitor and two transistors based on MagnaChip’s BCD process. The area of a unit cell is 37.743 75 μm2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs (power management ICs) using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and V5V, and a WL (word-line) driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V (=10 V) and V5V (=5 V) without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425 μm.

Implementation of Low Bandgap Reference Voltage Circuit for Power Management Applications

This paper proposes a low bandgap reference voltage circuit with low temperature coefficient and independent of suply voltage for applications to power management IC. This proposed circuit is design and implemented using the TSMC 0.35μm CMOS 2P4M process. Based on simulated and measured results , the chip size is 20.6000.680mm with power dissipation about 3.3mW, and the operation temperature range form 0Cto 100C with temperature coefficient about 9.29/ppmC. The chip suply voltage can from 2.9V to 3.3V with PSRR about 44.2 dB, and its output reference voltage can stable at 0.65V.

Study of Factors Contributing to Robust Copper Wire Bond on QFN

Copper wire interconnect is gaining momentum in mass production at rapid speed as the industry continue to mature into more robust copper wire bond process capability and at the same time has realized its cost benefits over gold wire interconnect . QFN (Quad Flat No-Lead packaging) has been in mass production for longer period in industry to support trend towards smaller packaging technologies, replacing other lead frame base or even substrate base packaging solution at rapid speed. Typical QFN 's thermal and electrical performance has been improved over the traditional lead frame base packaging and has become popular choice among designers to take advantage of the reduced form factors for application in cell phones, power management ICs and other portable consumer electronics.

The Research of the Power Supply System of Embedded Portable Devices

Portable devices are mostly powered by battery. With the products tending to the direction of light, thin, short and multi-functional integration, the power requirements of portable devices are increasing all the time, but the energy density of battery is far behind the speed, the improvement of performance relies heavily on the power management technology. Therefore, it’s needed that manage the power of whole system with the integrated viewpoint to reduce power consumption and extend the system work time. After the analysis and research for power management technologies, one kind of a combination of hardware and software power management solution is proposed. The power management IC with embedded Linux operating system's Dynamic Power Management technology, better to reduce system power consumption, meets the requirements of the power system supplied by portable equipment.

A New Power Management IC Architecture for Envelope Tracking Power Amplifier

A new supply modulator architecture for robust performance against the battery voltage variation is presented. The resulting modulator is an optimized power management integrated circuit (PMIC) for an envelope tracking (ET) power amplifier (PA). The basic topology of the PMIC is based on a hybrid switching amplifier combining a wideband class-AB buffered linear amplifier and a highly efficient switching-mode buck converter in a master-slave configuration. The additional boost converter regulates the supply voltage of the linear amplifier, while the supply of the buck converter is directly coupled to the battery. The proposed supply modulator achieves max/min efficiencies of 76.8/69.3% over the entire battery voltage range. The ET PA is operated at 4.5 V, providing higher output power, efficiency, and gain than at nominal 3.5-V design. The robust performance of the proposed PMIC is demonstrated.

P‐63: New Power Management Technology for Large AMOLED Displays

AbstractThere is growing interest in large AMOLED displays, but for proper operation and avoidance of display artifacts, large AMOLEDs have unique power requirements that extend beyond current generation displays. This paper presents a new small form factor single package multi‐output digital and analog power management IC that has been developed for large size AMOLED panel applications. Guidance is provided for optimization and desensitization of power sources for large AMOLED panels.

Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC Product

In advanced BEOL process, metal defect reduction plays an important role for Cp yield improvement. "Crown defect" is one of the killer defects. It develops in Litho process, forms after Aluminum etching, and finally turns out to be ring-type Al2O3 residue. Aluminum grain size is strongly related with crown defect performance. Especially for thick Aluminum film (>3μm), which is widely applied on high voltage power management IC product, it is a big challenge to control grain size and keep a relatively uniform film surface. In this paper, a study of the relationship between Aluminum grain size and crown defect is presented. Also, a novel approach to control the grain size is shown to reduce the crown defect for Cp yield improvement.

Evaluation of Packaging-Induced Performance Change for Small-Scale Analog IC

The impact of packaging-induced circuit performance changes for a small-scale integrated circuit (IC) smaller than 1.0 mm 2 has been evaluated by a new method with specially designed test chips. Analog circuits such as power management ICs for portable electronic devices are small-scale chips and require high-accuracy operation. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence, after which one distribution chart was reproduced from all of the measurement results. The present method enables the characteristic distribution on the chip surface to visualize not only the electrical parametric distribution but also the residual stress distribution, even though small-scale ICs have a limited number of bonding pads. In addition, a new method for evaluating the circuit performance change of an analog circuit due to stress-induced parametric changes is presented.

A Highly Integrated Power Management IC for Advanced Mobile Applications

Wireless communication now has the speed and power to converge seamlessly with other consumer and business electronics. However, battery technology has not kept pace with advancement in circuit technology. As a result, design of power management is becoming a more complex problem for this new generation of wireless devices with converged voice, data, and multimedia. In this paper, a highly integrated power management IC (PMIC) is presented which enables mobile devices that are more cost effective, thinner and more compact with better power efficiency. The overall architecture and system level design considerations are described. The design details of two key building blocks - low-dropout linear regulator (LDO) and switch-mode DC-DC converter - are also discussed, including a novel frequency compensation method for LDO.

Design of a Low Power, High Performance BICMOS Current-limiting Circuit for DC-DC Converter Application

A low power, high performance current-limiting circuit implemented in 0.6um BICMOS process, which has been successfully applied to the chip of high e-ciency, wide input voltage range DC-DC boost switch power management chip, is presented. The circuit as the core sub-block of the chip consists of current-limiting comparator, soft starting and slop compensation. The dynamic bias and slop compensation technology in current-limiting comparator is adopted to improve the performance and to reduce power consume. In this paper, the deign methodology and process of the circuit is analyzed in detail. The simulation and test results based HSPICE show: under the power supply of 3.3V, the circuit has the gain of 117dB and low quiescent current of 15UA. DOI: 10.2529/PIERS060817034009 With the rapid development of the integrated circuit technology, the requirement of low power consumption, small volume, low cost for portable and powered equipment such as MP3, PDA and digital camera can be satisfled impossibly, meanwhile, the new functions belonging to the \energy hunger and thirst type are increasing with day, so it is key issue in this fleld how to integrate these new functions in smaller volume and to prolong the service time of battery-operated equipments. At present, the switch-mode DC-DC converters have been widely used in power supply systems and are becoming a common building block in modern VLSI systems, which are taking place of LDO and will be the best solution because of its high e-ciency. Therefore, it is meaningful and better market prospect to research the power management IC of high e-ciency, low power. Figure 1 illustrates a simplifled boost dc-dc converter's functional block diagram. Its main function is to convert input dc voltage to higher output dc voltage with minimum power loss. The converter is composed of a power stage and feedback control circuits. VS is a battery voltage, which supplies input dc voltage, and is the boosted output dc voltage. The inductor L, diode D1, and capacitor C are ofi-chip components. Resistors R1 and R2 sense the output voltage and generate the scaled output voltage to the error amplifler. RLOAD is the load of the dc-dc converter.

Switch Bootstrapping for Precise Sampling Beyond Supply Voltage

Bootstrapped switches are used in a variety of applications including DC-DC converters, pipelined analog-to-digital converters and high voltage switches and drivers. Current work on highly integrated power management applications often requires the ability to measure voltage quantities that exceed the supply voltage in magnitude. This is primarily due to a basic need to maximize efficiency by running the power management IC on as low supply voltage as possible, while still maintaining the ability to sample and measure quantities from the surroundings that could well exceed the battery voltage. In this paper, a new bootstrapped switch is presented. The switch enables the precise sampling of input signals well greater than the chip supply voltage with no static power consumption, and without activating on-chip parasitic body diodes. The bootstrapped switch, presented here, is designed to sample an input signal with a 0-5.5-V range at a supply voltage of 2.75 V. Measurement data shows functionality for a 0-6-V input signal range with a supply voltage as low as 1.2 V

Buck or Boost Tracking Power Converter

A cascade of buck and boost converter is presented here. The control operates in a manner that the converter is either in buck or boost (BOB) mode on a cycle by cycle basis. It transitions between the modes seamlessly to provide a tracking power conversion function for modulating the power supply of a variable envelope radio frequency (RF) power amplifier. The control algorithm and its implementation using switched capacitor circuits is described. Simulation and measured experimental results including converter efficiency, tracking accuracy, and spectrum at the output of the RF power amplifier are provided. This control technique allows seamless transition between the buck and boost modes while tracking RF envelopes with bandwidth greater than 100 kHz, and maintaining extreme accuracy and extremely low ripple. The efficiency of this converter operating at 1.68 MHz is close to 90% over a wide range of conversion ratios. The area of the power converter is extremely small allowing this to be integrated into a cellular telephone. The controller was integrated as part of a larger power management IC as well as a discrete IC.