Power Efficient Design Research Articles

Low power and energy efficient design of ternary D-latch based on CNTFET-RRAM technology

Low power and energy efficient design of ternary D-latch based on CNTFET-RRAM technology

Design of floating point multiplier using approximate hybrid Radix-4/ Radix-8 booth encoder for image analysis

This paper presents a novel power efficient Hybrid floating point multiplier (HFPM) with approximate hybrid radix-4/radix-8 booth encoder. This approach efficiently increases the speed of operation and optimises hardware. Compared to existing HFPMs, the proposed HFPM utilises a novel hybrid radix-4/radix-8 booth encoder. The hybrid architecture reduces the computations by an average of k/3 for a k-bit 2’s complement representation by reducing the number of partial products. In addition, to achieve an area-efficient and power-efficient design, approximate computational units are added to the radix-8 booth encoder in the hybrid architecture with a slight reduction in accuracy. The efficiency of the approximate architecture is measured in scales of Error Rate (ER) and Normalized Error Distance (NED). The proposed design is implemented on Kintex 7 FPGA and realized on 45nm ASIC platforms. The experimental study shows that the proposed multiplier has utilised hardware (831 slice LUT, 828 LUT as logic) and consumed 6110 μm2 of area and 83 μW of power which is less as compared to existing floating point multipliers. The experimental results in terms of average Structural Similarity Index Measure (SSIM) is 0.98 which is better than the existing floating point multipliers are compared.

Power efficient ReLU design for neuromorphic computing using spin Hall effect

We demonstrate that a magnetic tunnel junction injected with a spin Hall current can exhibit linear rotation of the magnetization of the free-ferromagnet using only the spin current. Using the linear resistance change of the magnetic tunnel junction (MTJ), we devise a circuit for the rectified linear activation (ReLU) function of the artificial neuron. We explore the role of different spin Hall effect (SHE) heavy metal (HM) layers on the power consumption of the ReLU circuit. We benchmark the power consumption of the ReLU circuit with different SHE layers by defining a new parameter called the spin Hall power factor. It combines the spin Hall angle, resistivity, and thickness of the HM layer, which translates to the power consumption of the different SHE layers during spin-orbit switching/rotation of the free FM. We employ a hybrid spintronics-CMOS simulation framework that couples Keldysh non-equilibrium Green’s function formalism with Landau–Lifshitz–Gilbert–Slonzewski equations and the HSPICE circuit simulator to account for the diverse physics of spin-transport and the CMOS elements in our proposed ReLU design. We also demonstrate the robustness of the proposed ReLU circuit against thermal noise and a non-trivial power-error trade-off that enables the use of an unstable free-ferromagnet for energy-efficient design. Using the proposed circuit, we evaluate the performance of the convolutional neural network for MNIST datasets and demonstrate comparable classification accuracies to the ideal ReLU with an energy consumption of 75 pJ per sample.

Power efficient designs of CNTFET-based ternary SRAM

This paper presents three new power-efficient designs of ternary SRAM using carbon-nanotube-field-effect-transistors (CNTFETs). Two of the proposed ternary SRAM designs are cycle-operator based and the third design is buffer-based. The cycle operators and buffer used in the design of the proposed ternary SRAM consume low power as they use two power supplies for operation. Ternary logic implementation using CNTFETs is largely being used lately due to the advantages it provides in terms of reduced interconnect complexity and chip area. The proposed ternary SRAM designs are compared with the existing designs using HSPICE simulations that use a standard Stanford CNTFET model. All the three proposed designs show considerable improvement in power consumption for read and write operations than their existing counterparts in literature. The read, and write delays and noise margins of the proposed designs are also analysed and are found to be comparable to the existing designs.

TSPC-AVLS Based Low-Power 16/17 Dual Modulus Pre-Scaler Design

Dual modulus pre-scalers (DMPS) are programmable counters used in phase-locked loops (PLL). The dual modulus division capability improves the circuit functionality and can be used as a divider of N/N + 1 cycles, which can be controlled through a master input. This paper proposes power and area efficient divide-by-16/17 DMPS designs, which incorporate true single-phase clocking (TSPC) based D flip-flops, which consume less power with minimal area. Power reduction is achieved by integrating adaptive voltage level-source (AVLS) circuit to DMPS. The proposed-I divide-by-16/17 DMPS has been implemented by using TSPC based D flip-flops incorporating the AVLS technique. The proposed DMPS consumes 146.6 µW (34%) less power when compared to the reference architecture, in divide-by-16 mode. Further optimization of the pre-scaler design is done by using a minimum number of transistors, involving pushing the logic (AND) into the first stage of TSPC based D flip-flops which results in an area as well as power efficient design. The proposed-II circuit is realized by using optimized TSPC based D flip-flops, along with incorporation of the AVLS technique, resulting in a power efficient design. For instance, in divide-by-16 mode of operation, a 100 µW (21%) reduction in the total power is observed when a DMPS circuit is realized in CMOS 180 nm technology. Also, when the proposed DMPSs are realized in CMOS 45 nm technology, the same trend of power reduction is observed, which are analyzed at an operating frequency of 1 GHz. The circuits are realized in Cadence Virtuoso and simulated in Spectre.

Novel design of power-efficient quaternary logic gates using CNTFET

ABSTRACT This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs.

Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor

RISC-V set architecture is playing an increasingly important role in processor technology due to its open instructions which allow researchers to build and improve computing systems. However, many RISC-V architectures exist in multi-core architecture with complex designs, large area, and high-power consumption. This paper studies an open-source multi-core RISC-V processor in a simple design with less power consumption. The processor depends on an open-source single RISC-V core processor, Taiga. Two cores of Taiga are integrated on a single chip while addressing issues related to cache coherence, interconnect, and memory design. A solution has been developed to achieve data coherence between implemented caches and the main memory; its architecture depends on the snoopy protocol. A hardware-customized peripheral unit has been implemented to achieve the management process among operated cores’ tasks. For more consistent and highly controlled memory storage, the main memory unit has been designed in dual-port based on a specific protocol in the interface, and 8192 lines and word addressable unit. As the UART is common in several devices and processors for communication, the UART as a peripheral customized device has been appended for communication with other devices. The processor has been implemented in System Verilog HDL and extensively tested on various testbenches to ensure correct functionality. Hence, the system performance has been evaluated using the CoreMark benchmark, and achieved 4.605 CoreMark/MHz on Zedboard (FPGA Xilinx family) with a maximum operating frequency 98 MHz. The results indicate that the processor performs comparably to state-of-the-art multi-core processors, while offering a simpler and more power-efficient design. Overall, the research demonstrates the potentialof RISC-V architecture in creating a simple and power-efficient multi-core RISC-V processor.

Power Efficient Design a Compliant Robotic Leg Based on Klann's Linkage

This article presents the analysis and optimization of a compliant robotic leg based on Klann's linkage. This leg is specifically designed to efficiently distribute its power requirement over its complete motion cycle, avoiding large peaks in the energy drawn from the battery. The structural compliance of the leg will be shown to be able to both provide a satisfactory walking motion and a timely energy boost to help with the gait. Klann's linkage is selected here as the basic kinematic structure of the leg to demonstrate the proposed methodology, namely to combine in a single structure both a complex trajectory generation and energy storage/release. This work is first aiming at proposing a thorough kinematic analysis of that mechanism using planar screw theory. The latter will be shown to be able to efficiently provide the velocity equations of the linkage as well as its force input–output relationship and singularity conditions. In a second part of this article, the previous kinetostatic model will be used to design and optimize a compliant version of the leg optimizing the power required for the robot to move. Finally, experiments will be shown to support the proposed approach.

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications

Myocardial Infarction (MI) is a critical heart abnormality causing millions of fatalities worldwide every year. MI progress in three stages based on its severity causing several changes in an Electrocardiogram (ECG) signal. It is very critical to capture these variations, which requires continuous monitoring of the ECG signal of the patient. Therefore, it becomes imperative to develop a low power VLSI architecture to address the prognosis of MI. In this brief, for the first time, an area and power efficient design of a five stage classifier is proposed, which detects the progression of various stages of MI using ECG beats in real time. The proposed architecture has an area and total power utilization of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.38mm^{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.12~\mu W$ </tex-math></inline-formula> , respectively at SCL 180nm Bulk CMOS technology. The low power and area requirements and multiclass classification capability of the proposed design make it suitable to be used in wearable devices.

Design and Implementation of an Area and Power-efficient Reconfigurable Hearing Aid using Interpolated Sub-band Distribution Technique

A hearing aid is a compensatory device that helps in overcoming various hearing disabilities. Since different people possess different hearing problems and the requirement gets changed over time, it is necessary to design a reconfigurable hearing aid which is generic in nature such that it supports various hearing disabilities without modifying the hardware components. The objective of the paper is to implement a reconfigurable digital hearing aid which is hardware efficient and it is auto-adaptable to disabilities ranging from mild to severe intensities. Since multipliers and LUTs are power hungry elements, we have proposed a design which is multiplier less and LUT-less DA Architecture. The prototype filter is a FIR filter which is designed using LUT-less Distributed Arithmetic Algorithm that saves 64% of logic elements &amp; memory and 76% of power utilization. As it is a multiplier-less as well as LUT- less architecture, hence this can be claimed to be area and power efficient design. The delays and matching errors are within the standard limits which are accepted globally. The input audio spectrum is divided into three regions and for each region there are four different filter banks are proposed using interpolated sub-bands distribution. Xilinx System Generator is used to implement the proposed design. The proposed design requires least manual configuration for selection of filter banks for audiogram matching which also minimizes the trial-anderror method to establish the best match with the person’s audiogram.

A very low-power discrete-time delta-sigma modulator for wireless body area network

This paper proposes a very low-power discrete-time delta-sigma modulator (DTDSM) for the wireless body area network (WBAN) which deals with biomedical signals. The first stage integrator is optimized using correlated double sampling technique and is implemented using a high-gain designed telescopic operational transconductance amplifier (OTA) in order to maintain the proposed second-order DTDSM high resolution. In order to keep both stage integrators active and prevent ENOB loss, a very low power two-stage charge-steering amplifier is employed in the second stage integrator which leads to a power efficient design. Due to not high but enough voltage-gain of this type of amplifier, the proposed charge-steering-based integrator leads to a negligible loss of ENOB in comparison to passive integrators with no voltage gain which are commonly used in the second stage to reduce the total power. In fact, due to the combination of a high-gain OTA in first stage integrator and a low-power charge-steering amplifier in second stage, compromise between high resolution and low power consumption will be depicted.The proposed DTDSM is designed for a signal bandwidth of 50 kHz with an oversampling ratio of 128 for implantable biomedical devices in the MICS band. Simulations are done using TSMC 180 nm technology at a 1.8 V power supply. Simulation results illustrate that the designed modulator achieves an SNR of 56 dB which is equal to 9 bits of ENOB that is in the desired range for biomedical signals. The power consumption of this modulator is only 142 μW at a 12.5 MHz sampling frequency.

Tunable magnetic field source for magnetic field imaging microscopy

In this work, we present a novel, compact, power efficient and variable magnetic field source design for magnetic field imaging microscopy. The device is based on a pair of diametrically magnetized permanent magnet cylinders with electro-mechanical rotation control and ferrite flux homogenizers. A Hall probe and NV centers in diamond are used to demonstrate a proof of concept of a proposed magnetic field setup and to characterize the homogeneity of the produced magnetic field on a micrometer scale. Numerical simulation results are compared with experimental results showing good agreement of the distribution of the magnetic field in the setup. As a result, a magnetic field source with a tunable field amplitude in the range from 1 mT to 222 mT is demonstrated, achieving a magnetic field homogeneity of 2 ppm/μm or 0.5 μT/μm at 222 mT in a 25 × 25 μm field of view.

Energy Efficient Distance Computing: Application to K-Means Clustering

Distance computation between two input vectors is a widely used computing unit in several pattern recognition, signal processing and neuromorphic applications. However, the implementation of such a functionality in conventional CMOS design requires expensive hardware and involves significant power consumption. Even power-efficient current-mode analog designs have proved to be slower and vulnerable to variations. In this paper, we propose an approximate mixed-signal design for the distance computing core by noting the fact that a vast majority of the signal processing applications involving this operation are resilient to small approximations in the distance computation. The proposed mixed-signal design is able to interface with external digital CMOS logic and simultaneously exhibit fast operating speeds. Another important feature of the proposed design is that the computing core is able to compute two variants of the distance metric, namely the (i) Euclidean distance squared (L22 norm) and (ii) Manhattan distance (L1 norm). The performance of the proposed design was evaluated on a standard K-means clustering algorithm on the “Iris flower dataset”. The results indicate a throughput of 6 ns per classification and ∼2.3× lower energy consumption in comparison to a synthesized digital CMOS design in commercial 45 nm CMOS technology.

A 0.023–12 GHz ultra-wideband frequency synthesizer with FOMT of −251.8 dB

A fully integrated ultra-wideband fractional-N frequency synthesizer is presented in this paper. Ultra-wideband quadrature signals can be generated by an octave-wide fractional-N phase-locked loop (PLL) and an ultra-wideband local oscillator (LO) signal generator. An optimized dual-core voltage-controlled oscillator (VCO) is employed to maintain relatively constant loop parameters in the octave-wide operating range, while a negative-capacitance VCO (NC–VCO) is proposed to solve the frequency gap problem and enhance the design freedom of the wideband VCO. Moreover, a wide-range programmable multi-modulus divider (PMMD) with seamless switching and fractional division resolution is proposed for error-free division operation and quantization noise compensation in the fractional-N mode, respectively. Power-efficient design is mainly achieved by the presented hybrid LO generator with optimized divider topologies for different frequency ranges. Fabricated in a 55 nm CMOS process, 0.023–12 GHz continuous quadrature LO signals can be generated by the proposed frequency synthesizer which occupies an active area of 0.55 mm2 and consumes 75–104 mW from a 1.2 V supply. The measured phase noise is −108.1 dBc/Hz at 1 MHz offset from a 12 GHz carrier, and the I/Q phase error is less than 2.7° with FOMT of −251.8 dB.

Low power and area efficient design of fir filter using enhanced clock gating technique

The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various applications, but the number adders and multipliers occupy the design space since it increases the area and delay factors. The main aim is to reduce the number of adders and multiplier by various computational algorithms. The existing research work uses carry save accumulator with ripple carry adder and binary multiplier. In proposed method, the enhanced Vedic multiplication logic and improved carry lookahead adder logic improves the result. In Vedic multiplication algorithm, the number of adder logic is minimized by adding speculative Brent-kung adder logic in it. The fastest adder in VLSI circuit is CLA (Carry look ahead adder logic), which is improved by utilizing the result of reduced power consumption and delay. In this proposed research work, the power optimization is done by using enhanced clock gating technique. Here, area, power, and delay factors are measured and it is compared with conventional FIR filter design. The proposed method improves the result in the way of area, power, and delay. The whole FIR filter structure is designed and power optimized by connecting with an enhanced clock gating technique. This proposed design and simulate by using Xilinx ISE 14.5 and it is synthesize by ModelSim.

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.

High throughput SRAM design for improved computing in autonomous systems

PurposeHigh throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.Design/methodology/approachPower efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.FindingsBias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.Originality/valueThe proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter Using Power Efficient Multiply Accumulate Unit

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Ultra-Lightweight Block Cipher in Medical Internet of Things for Secure Machine-to-Machine Communication Using FPGA

With the swift growth of internet applications with the Internet of Things (IoT), medical sensors and online medical service has become mandatory part of every use case in the recent years. The health care system has become more connected with the increasing use of IoT devices, and these medical devices introduce vulnerabilities into health care organizations. Recently, there are significant cyber-threats against the medical IoT and some resisting elements of cryptosystem that cloud help to combat these threats. Hence, in medical IoT, security and privacy of patients are among the major areas of concern. However, such methods are very complex to implement in Field Programmable Gate Array (FPGA) platforms. This paper proposes an ultra-lightweight block ciphers (ULBC) for medical IoT applications. The first contribution of ULBC algorithm is to propose the chaotic Whale optimization (CWO) algorithm for key management, which improves the security and reduce hardware cost by reducing the number of iteration rounds. The second contribution is to introduce the flexible design of modified ULBC algorithm that provides an area, power and delay efficient design with attack free feature. The flexible design avoids the reconfigurable runtime, power; and it is surely different from existing block ciphers. Finally, the ULBC algorithm is synthesized in Xilinx tool with different FPGA families and the performance is compared with existing lightweight ciphers in terms of maximum clock frequency, power consumption and hardware utilization.

Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference

With advances in low power and battery-operated devices, concerns over power-efficient designs for system-on-chip devices is growing. Since some subsystems require to have both positive and negative voltage rails, it is essential to ensure this requirement is satisfied without increasing the cost and power consumption. This paper presents a novel Negative Level Shifter used to generate negative voltage levels from the positive DC power supply line. Additionally, an improved CMOS Voltage Reference generator based on a Resistorless Beta Multiplier is also proposed. The two circuits were tested under various conditions, and results validate the low-power operation of the proposed design. The proposed Negative Level Shifter required only 772 pW and has a delay equal to 4ns with a supply voltage of 0.3V. When assembled, both the reference voltage and the level shifter consume 8.5 nW with the supply voltage of 1V at room temperature.