Power Distribution Network Design Research Articles

Nonlinear Network Optimization—An Embedding Vector Space Approach

This paper proposes a normed-space vector representation of networks which allows defining evolutionary operators for network optimization that resemble continuous-space operators. These operators are employed here to build a genetic algorithm which becomes generic for the optimization of tree networks, without the requirement of any special encoding scheme. Such a genetic algorithm has been compared with several encoding-based genetic algorithms, on 25 and 50-node instances of the optimal communication spanning tree and of the quadratic minimum spanning tree, and has been shown to outperform all other algorithms in a stochastic dominance analysis. The proposed approach has also been applied to an electric power distribution network design (a multibranch problem), outperforming the results presented in a former reference (which have been obtained with an Ant Colony algorithm). The results of some landscape dispersion analysis suggest that the proposed normed-space network vector representation is analogous to some continuous-variable space dilation operations, which define favorable space coordinates for optimization.

An Efficient Power-Delivery Method for the Design of the Power Distribution Networks for High-Speed Digital Systems

In this paper, a new power distribution network (PDN) design method from a power delivery viewpoint is proposed. Two new parameters, the power delivery delay and the DeltaV time constant, are introduced to characterize the effects of the lead inductors and decoupling capacitors on the timely power delivery respectively for a high-speed PDN. The decoupling time of a PDN is accurately estimated from the power delivery delay introduced by the inductance of the discontinuities, the charge delivery speed, and the charge supply capacity of the decoupling capacitors are accurately characterized by the DeltaV time constant. Based on the two parameters, a complete and systematic power-delivery method for the design of a PDN is developed. The proposed design method is verified by SPICE, full-wave simulations, and measurements. For completion, some specific design considerations are also discussed in detail.

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.

Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1MHz to 3GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.

A constructal approach to power distribution networks design

A constructal approach to power distribution networks design

Analysis and Modeling of Hybrid Planar-Type Electromagnetic-Bandgap Structures and Feasibility Study on Power Distribution Network Applications

A unified 1D analysis model of hybrid planar-type electromagnetic-bandgap (EBG) structures is developed. Based on the analysis results, three types of hybrid design methods to reduce the cutoff frequency of the EBG structures are discussed, and design equations for their noise suppression bandwidths are derived. In order to simulate switching noise characteristics of the hybrid planar-type EBG structures, 2D circuit level models are developed and experimentally verified. With the developed circuit-level models and CMOS active switching devices, feasibility studies on the power distribution network design using the hybrid EBG structures are conducted. The hybrid EBG structure with series lumped chip inductors shows efficient noise suppression characteristics in both the frequency and time domains; however, it has potential limitations because of its generation of higher switching noise voltages depending on power supply connection configurations.

Design of EBG Power Distribution Networks With VHF-Band Cutoff Frequency and Small Unit Cell Size for Mixed-Signal Systems

Hybrid electromagnetic bandgap (EBG) power distribution networks (PDNs) with VHF-band cutoff frequency, small unit cell size, and wideband noise suppression characteristics are proposed. Commercial lumped chip inductors are used to implement inductive bridges between neighboring metal patches instead of conventional microstrip lines. A 1D analysis model of the EBG structure is developed to find a mathematical ground for the use of the lumped chip inductors in the EBG PDN designs. From 158 MHz to 4528 MHz a measured stopband bandwidth of 4.37 GHz is achieved with over -60 dB noise suppression levels.

Design Methodology for Global Resonant ${\rm H}$-Tree Clock Distribution Networks

Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described, supporting the design of low power, skew, and jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is presented that demonstrates the design of a two-level resonant H-tree network, distributing a 5-GHz clock signal in a 0.18-mum CMOS technology. This example exhibits an 84% decrease in power dissipation as compared to a standard H-tree clock distribution network. The design methodology enables tradeoffs among design variables to be examined, such as the operating frequency, the size of the on-chip inductors and capacitors, the output resistance of the driving buffer, and the interconnect width. A sensitivity analysis of resonant H-tree clock distribution networks is also provided. The effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing and power consumption is described

Power Distribution Network Design for VLSI [Book Review

Power Distribution Network Design for VLSI [Book Review

Impedance characteristics of power distribution grids in nanoscale integrated circuits

The essential design characteristic of nanoscale integrated circuits is increased interconnect complexity. Conductors at different levels of the interconnect hierarchy have highly different physical and, consequently, electrical characteristics. These interconnect lines also exhibit inductive behavior due to enhanced switching speed of nanoscale devices, making interconnect design and analysis difficult. The design of robust and area efficient power distribution networks for high-speed integrated circuits has therefore become a challenging task. The impedance characteristics of multilayer power distribution grids and the relevant design implications are the subject of this paper. The power distribution network spans many layers of interconnect with disparate electrical properties. Unlike single-layer grids, the electrical characteristics of multilayer grids vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low-resistance upper layers to the low-inductance lower layers. The inductance of a multilayer grid therefore decreases with frequency, while the resistance increases with frequency. The lower layers of multilayer power grids provide a low-inductance current path, significantly reducing the grid impedance at high frequencies. Multilayer power distribution grids extend to the lower interconnect layers, exhibiting superior high-frequency impedance characteristics as compared to power distribution grids built exclusively within the upper, low-resistance metal layers. A significant share of metal resources to distribute the global power should therefore be allocated to the lower metal layers. An analytic model is also presented to determine the impedance characteristics of a multilayer grid from the inductive and resistive properties of the comprising individual grid layers.

Power distribution networks for system-on-package: status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.

Modeling, Analysis and Design of Resonant Free Power Distribution Network for Modern Microprocessor Systems

This paper presents design-oriented analysis of the power distribution network (PDN) for high performance microprocessor systems to realize the resonant free, close to flat output impedance magnitude over a wide frequency range. Based on the frequency domain analysis, closed form design equations and parametric curves relating the system parameters are derived. A systematic method of estimating the optimum parameters of the decoupling capacitors used in a single or multistage PDN is described to realize the output impedance of specified magnitude for the noise-free, and critically damped voltage at the microprocessor core. The design examples and simulation results are discussed to demonstrate the application of the design equations and parametric curves.

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.

Constructal tree shaped networks for the distribution of electrical power

In this paper, we extend to the design of electric power distribution networks the constructal method of deducing the multiple dimensions of the network from the maximization of global system performance. Unlike earlier constructal designs of tree shaped networks, where the global objective was minimization of flow resistance and exergy destruction, in the present study, the global objective is minimization of the present worth total cost. The first half of the paper is a detailed account of all the components of the distribution system (hierarchy, voltage levels, lines, transformers) and the associated cost components that make up the global cost function. Emphasis is placed on the relations between length scales (radii, or reaches) at every voltage level and the costs of components and assemblies of components at every level and, ultimately, at the global level. It is shown that the global cost depends on multiple length scales, the load density (power consumption per unit of territory served) and the operating and economic characteristics of the voltage lines and transformers. Tradeoffs between the costs of lines and transformers exist at every voltage level, and this permits the multiple minimization of the global cost function. The optimized radii for each voltage level of the network are reported: they decrease at their own rates as the load density increases.

Modeling and Heuristic Worst-Case Performance Analysis of the Two-Level Network Design Problem

This paper studies a multi-facility network synthesis problem, called the Two-level Network Design (TLND) problem, that arises in the topological design of hierarchical communication, transportation, and electric power distribution networks. We are given an undirected network containing two types of nodes—primary and secondary—and fixed costs for installing either a primary or a secondary facility on each edge. Primary nodes require higher grade interconnections than secondary nodes, using the more expensive primary facilities. The TLND problem seeks a minimum cost connected design that spans all the nodes, and connects primary nodes via edges containing primary facilities; the design can use either primary or secondary edges to connect the secondary nodes. The TLND problem generalizes the well-known Steiner network problem and the hierarchical network design problem. In this paper, we study the relationship between alternative model formulations for this problem (e.g., directed and undirected models), and analyze the worst-case performance for a composite TLND heuristic based upon solving embedded subproblems (e.g., minimum spanning tree and either Steiner tree or shortest path subproblems). When the ratio of primary to secondary costs is the same for all edges and when we solve the embedded subproblems optimally, the worst-case performance ratio of the composite TLND heuristic is 4/3. This result applies to the hierarchical network design problem with constant primary-to-secondary cost ratio since its subproblems are shortest path and minimum spanning tree problems. For more general situations, we express the TLND heuristic worst-case ratio in terms of the performance of any heuristic used to solve the embedded Steiner tree subproblem. A companion paper develops and tests a dual ascent procedure that generates tight upper and lower bounds on the optimal value of a multi-level extension of this problem.

A Dual-Based Algorithm for Multi-Level Network Design

Given an undirected network with L possible facility types for each edge, and a partition of the nodes into L levels or grades, the Multi-level Network Design (MLND) problem seeks a fixed cost minimizing design that spans all the nodes and connects the nodes at each level by facilities of the corresponding or higher grade. This problem generalizes the well-known Steiner network problem and the hierarchical network design problem, and has applications in telecommunication, transportation, and electric power distribution network design. In a companion paper we studied alternative model formulations for a two-level version of this problem, and analyzed the worst-case performance of several heuristics based on Steiner network and spanning tree solutions. This paper develops a dual-based algorithm for the MLND problem. The method first performs problem preprocessing to fix certain design variables, and then applies a dual ascent procedure to generate upper and lower bounds on the optimal value. We report extensive computational results on large, random two-level test problems (containing up to 500 nodes, and 5,000 edges) with varying cost structures. The integer programming formulation of the largest of these problems has 20,000 integer variables and over 5 million constraints. Our tests indicate that the dual-based algorithm is very effective, producing solutions that are within 0.9% of optimality.

Power distribution network design aided by an expert system

The next couple of years will see the need for replacement of a large amount of life-expired switchgear on the UK 11 kV distribution system. Latest technology and alternative equipment have made the choice of replacement a complex task. In this article, an expert system is presented as an aid to the decision process for the design of the 11 kV power distribution network

Optimal design of two-voltage power distribution networks

A method for the optimal design of two-voltage power networks is presented. Since the optimization problem is compounded of two overlapping N P -hard problems, the proposed method is a combination of an exact tree-search technique with a heuristic procedure, adjusted to the requirements of repetitive use. The algorithm shows good performance, being fast and accurate, as confirmed by the results of computational tests and heuristic error estimation based on a statistical approach.