Improvement In Power-delay Product Research Articles

New Approach in Booth Decoder/Encoder and 5-2 Compressor for Multipliers

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65[Formula: see text][Formula: see text]W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74[Formula: see text][Formula: see text]W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09[Formula: see text][Formula: see text]m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.

CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques

As technology advances, electronic circuits are more vulnerable to errors. Soft errors are one among them that causes the degradation of a circuit’s reliability. In many applications, protecting critical modules is of main concern. One such module is Fast Fourier Transform (FFT). Real FFT (RFFT) is a memory-based FFT architecture. RFFT architecture can be optimized by its processing element through employing several types of adder and multipliers and an optimized memory usage. It has been seen that various blocks operate simultaneously in many applications. For the protection of parallel FFTs using conventional Error Correction Codes (ECCs), algorithmic-based fault tolerance (ABFT) techniques like Parseval checks and its combination are seen. In this brief, the protection schemes are applied to the single RAM-based parallel RFFTs and dual RAM-based parallel RFFTs. This work is implemented on platforms such as field programmable gate arrays (FPGAs) using Verilog HDL and on application-specific integrated circuit (ASIC) using a cadence encounter digital IC implementation tool. The synthesis results, including LUTs, slices registers, LUT–Flip-Flop pairs, and the frequency of two types of protected parallel RFFTs, are analyzed, along with the existing FFTs. The two proposed architectures with the combined protection scheme Parity-SOS-ECC present an 88% and 33% reduction in area overhead when compared to the existing parallel RFFTs. The performance metrics like area, power, delay, and power delay product (PDP) in an ASIC of 45 nm and 90 nm technology are evaluated, and the proposed single RAM-based parallel RFFTs architecture presents a 62.93% and 57.56% improvement of PDP in 45 nm technology and a 67.20% and 60.31% improvement of PDP in 90 nm technology compared to the dual RAM-based parallel RFFTs and the existing architecture, respectively.

Adiabatic technique based low power synchronous counter design

<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for realizing high-information density logic systems and high-operating speed systems. In this paper, a design for standard ternary inverter (STI), ternary NAND (TNAND), ternary NOR (TNOR) using carbon nanotube field effect transistors (CNTFETs) is proposed in which a p-type dynamic diode is used with the goal of lowering the energy consumption expressed as power delay product (PDP) and thereby reducing battery usage. Additionally, the basic arithmetic operations are then performed using proposed ternary logic circuits, which can be extended to realize more complex operations. The proposed designs are simulated in HSPICE using a 32 nm Stanford CNTFET model. With respect to variation in process parameters, the reliability of the proposed STI circuit is examined. Simulation results verify that the proposed designs show improvement in terms of power consumption and power delay product (PDP) compared to the other CNTFET based ternary logic circuits. Moreover, less variations are observed in power and PDP of the proposed logic gates with variation in process parameters, capacitance, temperature, frequency and supply voltage. The proposed circuit designs of STI, TNAND, TNOR, ternary half adder (THA), ternary multiplier (TMUL) show 78 %, 98 %, 99 %, 99 %, 99 % improvement in PDP respectively, as compared to the conventional CNTFET based circuit designs and 99 % PDP improvement in all proposed circuits compared to CNTFET based logic circuits with resistive load.

SAMA: Self-adjusting multi-cycle approximate adder

Approximate computing is a promising approach that leads to a better compromise between power and delay by trading an acceptable level of accuracy in inherently error resilient applications. In this paper, we present a runtime accuracy configurable approximate adder that can operate in both approximate and exact modes. It provides a better compromise between power, delay, and accuracy compared with state-of-the-art approximate adders at high accuracies. Our evaluations show that the proposed adder can make up to 45% and 79% improvements in power-delay product (PDP) and energy-delay product (EDP), respectively, compared with state-of-the-art approximate adders, at high accuracies. In the accurate mode, the improvements in the PDP and EDP are up to 58% and 82%, respectively. The use of the proposed adder in an image processing application and in a mean-squares prediction algorithm confirms its superiority over existing circuits in terms of PDP and EDP.

Adiabatic logic based shift registers for low energy IoT architecture—Design and contemplation

AbstractShift register is one of the important components in any digital circuit. By improving the performance of shift register, one can improvise the whole system performance. Shift registers are the basic memory units and data transfer devices in IoT applications. The efficacy of computing devices depends on the performance of arithmetic circuits, including shift registers. Adiabatic logic has been proposed as anew computing platform to develop power‐efficient IoT devices. This paper presents low power adiabatic shift registers. The design of shift registers uses D flipflop, based on DC‐DB PFAL (direct‐current diode based positive feedback adiabatic logic). Performance parameters of the presented circuits are analyzed for transistor count, power dissipation, latency, and PDP (power delay product). Simulations are run for all the presented circuits at 180nm and 45nm technology nodes. It is found that the proposed parallel in parallel out shift register (PIPO) design outperforms with the improvement in PDP as 53%, 53%, and 57% compared to theserial in serial out (SISO), serial in parallel out (SIPO), and parallel inserial out (PISO) shift registers respectively at 100MHz and 45 nm technology node. Further, the proposed PIPO shift register shows improved performance than the other designs in the literature.

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation

Approximate computing (AC) has been considered as a promising paradigm to improve the energy-efficiency of computing hardware for error-tolerant applications, with negligible quality degradation to the output. Dividers frequently limit the performance of a computing system; however, they have not received as much attention as multipliers and adders in AC. In this paper, an energy-efficient and high-performance approximate divider is proposed based on logarithmic conversion and piecewise constant approximation. In this design, the range for the conversion between binary and logarithmic numbers is first expanded from <inline-formula> <tex-math notation="LaTeX">$\mathbf {[{0,1}]}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$\mathbf {[-0.5,1]}$ </tex-math></inline-formula>. A heuristic search algorithm is then devised to find the most accurate constant set to approximate the reciprocal of the divisor, by minimizing a statistical error. The hardware implementation is presented for both floating-point (FP) and integer dividers. With a high configurability, the proposed divider results in a mean relative error distance (MRED) from 2.78&#x0025; to 0.046&#x0025;, indicating a high accuracy among state-of-the-art approximate dividers. Compared to the half-precision FP divider, the proposed divider with a MRED of 0.74&#x0025; can achieve nearly <inline-formula> <tex-math notation="LaTeX">$\mathbf {90\times }$ </tex-math></inline-formula> improvement in PDP. Moreover, compared to state-of-the-art approximate dividers, the proposed design is in the Pareto Frontier in terms of power delay product (PDP) and MRED. The three image processing application results demonstrate that the proposed divider can result in the highest peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) even with truncation.

Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node

ABSTRACT Due to the continuous scaling of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) devices over the past few decades, power consumption has increased tremendously. To reduce power dissipation at lower technology nodes, digital logic circuits are designed with modern (FinFET) devices. In this paper, FinFET INDEP (input dependent) technique-based short gate (SG) FinFET Adder circuits are proposed at 10 nm technology node. The performance comparison of INDEP technique-based adder circuits is done with the SG FinFET adder circuits. The analysis of adder circuits is performed first in terms of functional verification (transient characteristics) and finally for different performance parameters such as propagation delay, power dissipation and power delay product (PDP). The proposed FinFET INDEP technique proves as one of the best leakage reduction techniques for FinFET adder circuits at lower technology nodes. To test the reliability of the circuits, Monte Carlo analysis is also performed. The PDP is improved by 16.8% and 13.73% in INDEP SG FinFET half adder(HA) and INDEP SG FinFET full adder(FA) at 10 nm technology, respectively, in comparison with the ones without INDEP technique. The Monte Carlo simulation results with 3σ Gaussian distribution at ±10% process, voltage and temperature variations show the improvement in PDP in case of SG INDEP FinFET FA and SG INDEP FinFET HA circuit in comparison to SG FinFET FA and FinFET HA circuit, respectively. Simulation is performed using HSPICE tool at 10 nm process technology node.

Design and performance analysis of an ultra‐high‐speed 5‐2 compressor

AbstractA novel ultra‐high‐speed 5‐2 compressor is presented and discussed in this paper. The proposed structure is developed by modifying the truth table focusing on the carry rippling problem. By reducing the number of the states in the truth table and the complexity of the structure, the total delay is reduced while the power and active area are also improved. The proposed compressor is compared with the best recently reported ones where the designed architecture shows 9%–80% improvement in power delay product (PDP). For a better demonstration of the advantages, the proposed structure is placed in the body of a 16 × 16‐bit multiplier and is compared with the other multipliers consisting of the other 5‐2 compressor architectures. The results indicate an improvement equal to 13%. It must also be mentioned that the gate‐level delay calculation is emphasized in this paper, where a precise estimation method is utilized considering the capacitances at the middle‐stage nodes. Based on the calculations, the designed circuit has the minimum gate‐level delay compared to the other related works due to its minimal intermediate connections. For simulating the proposed structure, a standard CMOS 0.18‐μm process along with HSPICE software is used, where the results show a delay of 266.5 ps with a power consumption of 164 μw.

A high‐performance full swing 1‐bit hybrid full adder cell

This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.

Power optimisation of single phase clocked feedback D flip-flop for CDMA

ABSTRACT A low power flip-flop is demanding delay element in digital sigma delta modulator of DAC system. This paper highlights power optimisation of single-phase clocked feedback D flip-flop using various optimisation techniques like clock gating, MTCMOS etc. In this scenario, clock gating using GDI and single-phase clocked inverter is invented to avoid unwanted no data transitions of flip-flop, also proposed type is compared with existing techniques. In addition to this, full swing GDI (gate-Diffusion Input) cell itself is modified by single phase clocked inverter to minimise threshold voltage drop and unwanted spikes at the output. There is trade off in area, speed and power. This work is based on power optimisation with favourable speed and area. Flip-flop is verified for clock frequency of 50 MHz as well as CDMA (Code Division Multiple Access) frequency of 1.6 MHz. Analysis is carried out in SPECTRE simulator of CADENCE environment with 180 nm technology supplied by AMS. Not only power but delay is also measured to check the performance of flip-flop. Proposed circuit gives 92.8% power and power delay product improvement.

A high-speed and scalable XOR-XNOR-based hybrid full adder design

This work presents the design of a scalable and full-swing Full Adder (FA) based on the XOR-XNOR module. The performance of the design has been compared with eleven existing state-of-the-art FAs. The proposed FA obtains 19.35% improvement in Silicon area, 33.59% improvement in Average Power, 36.15% improvement in Propagation Delay, 56.22% improvement in Area Delay Product (ADP), and 57.59% improvement in Power Delay Product compared to the conventional Mirror CMOS FA. Moreover, performance parameters have been examined in wide adder structures by extending the FAs to 32-bits without adding level restoring buffers in the intermediate stages. The obtained simulation data suggest that the proposed FA and 5 out of the 11 existing FAs can be practically scaled up to 32-bits. The proposed FA showed superior performance in the 32-bit operation. Because of the improved features, the proposed hybrid FA can be a reliable and superior alternative to existing FAs.

Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

ABSTRACT This paper proposed a domino logic namely “Gated Clock and Revised Keeper (GCRK)” domino logic 16 nm CMOS technology. The proposed domino logic has a revised keeper circuitry to reduce the power consumption in the circuit. A multiplexer is added in the GCRK design for gating the clock signal during sleep mode while maintaining the state of the domino logic. Total power consumption, delay and power-delay-product (PDP) of 16-bit OR gate GCRK domino logic and existing domino logic designs are calculated and compared. The existing domino logic techniques considered in this paper are – Leakage tolerant multiphase keeper domino logic (LTMK), high-speed domino logic (HSD), clock delayed sleep mode domino logic (CDSMD), grounded pmos keeper domino logic (GPKD) and foot driven stack transistor domino logic (FDSTDL). The proposed design shows significant improvement in PDP with respect to the existing designs. The PDP of proposed design (LTMK) is improved to 99.98%, 88.75%, 11.54% and 37.11% as compared to LTMK, HSD, GPDK and FDSTDL designs, respectively. Noise analysis and Monte Carlo simulation show that the proposed design is immune to noise and reliable under different parametric variations.

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design

In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder is the primary computational arithmetic block in numerous of the computing executions and hence is the critical component of ALU.Various existing full adders proposed in literature fail to accomplish low power delay product (PDP) and lacks driving strength when used in chainsstructure.In this paper two new hybrid full adders have been proposedwith an aim to achieve low PDP.Further the paper proposesripple carry adder (RCA) in chainstructure using triplet design approach to improve the driving strength. Fivedifferent hybrid full adders topologies have been implementedto build 4-bit RCA adder in regular and triplet logic design and PDP improvement is obtained in triplet design approach. All the simulations are done on 45nm technology and performance analysis done over the voltage range 0.6 V to 1.2V in Cadence Virtuoso simulation software. Simulation results are obtained to show that delay and PDP has improved in triplet designing and the proposed hybrid adders represents least PDP among other implemented reference circuits.

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI hierarchical array architecture for balanced (2 n -1, 2 n , 2 n +1) and unbalanced (2 k -1, 2 k , 2 k +1) word-length moduli are proposed which is capable of handling signed input numbers. Balanced 2 n -1 SRM is used as a reference to design an unbalanced 2 k -1 and 2 k +1. The synthesized results show that the proposed 2 n -1 SRM architecture achieves 17% of the area, 26% of speed and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the literature. The proposed 2 n +1 SRM architecture achieves 23% of the area, 20% of speed and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel hierarchical approach adopted for the design which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2 n -1, 2 n , 2 n +1} special moduli set based RNS processor and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA).

An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger

This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher Ion: Ioff ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.