Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

Abstract

ABSTRACT This paper proposed a domino logic namely “Gated Clock and Revised Keeper (GCRK)” domino logic 16 nm CMOS technology. The proposed domino logic has a revised keeper circuitry to reduce the power consumption in the circuit. A multiplexer is added in the GCRK design for gating the clock signal during sleep mode while maintaining the state of the domino logic. Total power consumption, delay and power-delay-product (PDP) of 16-bit OR gate GCRK domino logic and existing domino logic designs are calculated and compared. The existing domino logic techniques considered in this paper are – Leakage tolerant multiphase keeper domino logic (LTMK), high-speed domino logic (HSD), clock delayed sleep mode domino logic (CDSMD), grounded pmos keeper domino logic (GPKD) and foot driven stack transistor domino logic (FDSTDL). The proposed design shows significant improvement in PDP with respect to the existing designs. The PDP of proposed design (LTMK) is improved to 99.98%, 88.75%, 11.54% and 37.11% as compared to LTMK, HSD, GPDK and FDSTDL designs, respectively. Noise analysis and Monte Carlo simulation show that the proposed design is immune to noise and reliable under different parametric variations.