Chip Power Consumption Research Articles

ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks

A synthesis approach based on Answer Set Programming (ASP) for heterogeneous system-on-chips to be used in distributed camera networks is presented. In such networks, the tight resource limitations represent a major challenge for application development. Starting with a high-level description of applications, the physical constraints of the target devices, and the specification of network configuration, our goal is to produce optimal computing infrastructures made of a combination of hardware and software components for each node of the network. Optimization aims at maximizing speed while minimizing chip area and power consumption. Additionally, by performing the architecture synthesis simultaneously for all cameras in the network, we are able to minimize the overall utilization of communication resources and consequently reduce power consumption. Because of its reconfiguration capabilities, a Field Programmable Gate Array (FPGA) has been chosen as the target device, which enhances the exploration of several design alternatives. We present several realistic network scenarios to evaluate and validate the proposed synthesis approach.

Transformer-Feedback Interstage Bandwidth Enhancement for MMIC Multistage Amplifiers

The transformer-feedback (TRFB) interstage bandwidth enhancement technique for broadband multistage amplifiers is presented. Theory of the TRFB bandwidth enhancement and the design conditions for maximum bandwidth, maximally flat gain, and maximally flat group delay are provided. It is shown that the TRFB bandwidth enhancement can provide higher bandwidth compared to the conventional techniques based on reactive impedance matching networks. A three-stage low-noise amplifier (LNA) monolithic microwave integrated circuit with the TRFB between its consecutive stages is designed and implemented in a 0.1- $\mu{\hbox {m}}$ GaAs pHEMT process. The TRFB is realized by coupling between the drain bias lines of transistors. The reuse of bias lines leads to bandwidth enhancement without increasing the chip area and power consumption. The LNA features average gain of 23 dB and 3-dB bandwidth of 11–39 GHz. It provides a noise figure of 2.1–3.0 dB and an output 1-dB compression point of 8.6 dBm, while consuming 40 mA of current from a 2-V supply.

Design of a faster 8T SRAM memory cell

This paper discusses the design of read/write assist circuits which are used in a SRAM cell’s design to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The basic operations, SNM concept, and write margin of an SRAM are described theoretically as well as measured in simulation. The write assisted circuit, the Negative Bit-line Voltage Bias scheme, is discussed and implemented at transistor level using a six-transistor (6T) SRAM cell. With the write assisted circuit, the implemented memory array successfully performs a write operation, the condition in which the same operation would fail without the write assisted circuit. During the simulation, this write assisted circuit helps to achieve the negative bias voltage of -70mV on the SRAM’s bit- lines. The cost overhead includes chip area, power consumption and chip area

A Novel Approach For Design Of Pulse Triggered Flip-Flop To Enhance Speed And Power

In VLSI Technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered flip-flops (P-FF) have single latch and hence simpler in circuit complexity. Use of Explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition. Dual edge triggering can be adopted as it consumes less power as compared to single edge triggering. Also conditional discharge technique can be used to reduce switching activity. The work is done in tanner tool software. KeywordsFlip-Flop, Pulse Triggered, Dual Edge __________________________________________________*****_________________________________________________

SI-Studio, a layout generator of current mode circuits

This work is the answer to the so far unsolved problem of generation of integrated circuits topography for current mode circuits. Synthesis methods corresponding to already existing digital methods are proposed. Among others – the following has been shown: a digital adaptation of the row strategy for analog cell design, as well as performance control of the circuits with respect to chip area, power consumption and speed operation. The proposed algorithms are integrated with the already-existing tools for automatic layout generation of analog circuits with behavioral description at the beginning. At each stage of the synthesis process – an architecture description in the VHDL-AMS language was used, which so far has been not useful to synthesize. On the basis of the elaborated expert system, layouts of a filter pair and a filter bank were generated. The circuits were fabricated in TSMC 0.18μm CMOS technology and results of measurements are presented. The elaborated approach makes a contribution to the realization of current mode circuits with complexity not achievable up to now.

A new power profiling method and power scaling mechanism for energy-aware NetFPGA gigabit router

Today the ICT industry accounts for 2–4% of the worldwide carbon emissions that are estimated to double in a business-as-usual scenario by 2020. A remarkable part of the large energy volume consumed in the Internet today is due to the over-provisioning of network resources such as routers, switches and links to meet the stringent requirements on reliability. Therefore, performance and energy issues are important factors in designing gigabit routers for future networks. However, the design and prototyping of energy-efficient routers is challenging because of multiple reasons, such as the lack of power measurements from live networks and a good understanding of how the energy consumption varies under different traffic loads and switch/router configuration settings. Moreover, the exact energy saving level gained by adopting different energy-efficient techniques in different hardware prototypes is often poorly known. In this article, we first propose a measurement framework that is able to quantify and profile the detailed energy consumption of sub-components in the NetFPGA OpenFlow switch. We then propose a new power-scaling algorithm that can adapt the operational clock frequencies as well as the corresponding energy consumption of the FPGA core and the Ethernet ports to the actual traffic load. We propose a new energy profiling method, which allows studying the detailed power performance of network devices. Results show that our energy efficient solution obtains higher level of energy efficiency compared to some existing approaches as the upper and lower bounds of power consumption of the NetFPGA Openflow switch are proved to be 30% lower than ones of the commercial HP Enterprise switch. Moreover, the new switch architecture can save up to 97% of dynamic power consumption of the FPGA chip at lowest frequency mode.

A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm 2 .

Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of −13.5 dBm

A reconfigurable 256 × 256 image sensor controller that is compatible for depth measurement

This paper presents an image sensor controller that is compatible for depth measurement, which is based on the continuous-wave modulation time-of-flight technology. The image sensor controller is utilized to generate reconfigurable control signals for a 256 × 256 high speed CMOS image sensor with a conventional image sensing mode and a depth measurement mode. The image sensor controller generates control signals for the pixel array to realize the rolling exposure and the correlated double sampling functions. An refined circuit design technique in the logic level is presented to reduce chip area and power consumption. The chip, with a size of 700 × 3380 μm2, is fabricated in a standard 0.18 μm CMOS image sensor process. The power consumption estimated by the synthesis tool is 65 mW under a 1.8 V supply voltage and a 100 MHz clock frequency. Our test results show that the image sensor controller functions properly.

Review of Leakage Power Reduction in CMOS Circuits

Recent Technological advances in Wireless Communication has shown the convergence of terminals and networks that support multimedia and real-time applications. This obviously puts an immense pressure on battery of any mobile device. The CMOS has been the leading technology in today’s world of mobile communication due to its low power consumption. Reduction of leakage power in CMOS has been the research interest for the last couple of years. In CMOS integrated circuit design there is an important trade-off between technology scaling and static power consumption. In today’s CMOS technology the leakage power consumption plays a significant role. As we approaching to nano-scale design the total chip power consumption becomes dependent on leakage power. Increasing the battery life in mobile wireless communication and mobile computing and similar other applications is the topic of research now-a days... Further, since the leakage of battery exists even when devices are in idle state makes leakage power loss most critical in CMOS VLSI circuits. Many techniques have been evolved to tackle the problem and its still in progress. This paper mainly focuses on the review of various works done in this field till today’s date. Further a review of recent work done on a new technique LSSR (Lector Stack State Retention Technique) is discussed in the paper.

Prototype Filter Design Approaches for Near Perfect Reconstruction Cosine Modulated Filter Banks - A Review

Cosine Modulated Filter Banks (CMFB) are very popular among the different maximally decimated filter banks due to their design ease and simplicity in implementation and the property that all the coefficients of all the filters are real. All the analysis and synthesis filters are derived from one or two prototype filters. Hence, recently, the design of the prototype filter in a CMFB has become a subject of interest in the field of multirate signal processing. Perfect Reconstruction (PR) filter banks are those which can produce at the output, a weighted delayed version of the input. But in most of the applications a near perfect reconstruction (NPR) is sufficient. This can reduce the computational complexity. Different approaches developed for the efficient and optimal design of the prototype filter in a NPR orthogonal CMFB are studied, classified and summarized in this paper. In today's applications, less space and low power consumption are very essential. When the different design approaches for the design of the prototype filter in CMFB are compared, it is observed that the one using frequency response masking(FRM) and meta-heuristic optimization techniques gives better performance in terms of implementation complexity, which in turn can lead to reduced chip size and power consumption. It is hoped that this review will be highly beneficial to the researchers working in the area of multirate signal processing. At the end, we also propose some novel design approaches for the design of low complexity prototype filter using FRM technique.

Energy, Exergy, and Friction Factor Analysis of Nanofluid as a Coolant for Electronics

Power dissipation, chip power consumption, and heat flux in electronic devices have been steadily increasing over the past decade, creating a need for improved methods of cooling them. Nanofluids can be used as coolant for these electronics to improve their thermal performance. This paper presents an analysis of the energy, exergy, and frictional efficiencies of different nanofluids that are used to cool electronics. This was done by creating an analytical model in which different nanofluids flowed (at 0.5 m/s) through a rectangular-shaped microchannel heat sink (with a constant heat flux). These different nanofluids consisted of water as a base fluid, with 0.4 to 2.0 vol % of copper oxide (CuO), aluminum oxide (Al2O3), and titanium dioxide (TiO2) nanoparticles. The results generally showed that thermal resistance decreases as the volume fraction of nanoparticles is increased. The CuO-water nanofluid was found to be the best coolant in terms of both minimizing thermal resistance and maximizing the pressur...

Spectral estimation for long‐term evolution transceivers using low‐complex filter banks

For mobile user equipments (UEs), a careful power management is essential. Despite this fact, quite an amount of energy is wasted in today's UEs’ analogue (AFEs) and digital frontends (DFEs). These are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. These requirements define a worst-case scenario still ensuring reliable communication. In a typical receiving process the actual requirements can be considered as less critical. Knowledge about the actual environmental spectral conditions allows to reconfigure both frontends to the actual needs and to save energy. In this paper, the authors present a highly efficient generic spectrum sensing approach, which allows to collect information about the actual spectral environment of an UE. This information can be used to reconfigure both the AFE and DFE, thus endowing them with increased intelligence. A low-complex multiplier free filter bank extended by an efficient power calculation unit will be introduced. They also present simulation results, which illustrate the performance of the spectrum sensing approach and a complexity comparison with different well-known implementations is given. Furthermore, estimates on the chip area and power consumption based on a 65 nm CMOS technology database are provided, considering the Smarti4G chip as a reference.

Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology.

QBNoC: QoS-aware bufferless NoC architecture

Chip area and power consumption are the main restrictions for Network-on-Chip (NoC), a high proportion of which is consumed by the buffers in the routers. Therefore, bufferless NoC, which completely eliminates in-router buffers, has been proposed. However, the existing bufferless NoC designs do not provide Quality-of-Service (QoS) guarantee. In this paper, we propose a QoS-aware Bufferless NoC, named QBNoC. QBNoC employs hybrid switching mechanism, namely circuit switching mechanism for real-time application and wormhole switching mechanism for other applications. Besides, in order to decrease the deflection probability and thus improve the performance of the network, we propose a new output port allocation policy, named Two-Stage Allocation (TSA). Furthermore, new router architecture with shorter critical path is designed for QBNoC. The evaluation results show that by efficiently exploiting resources, our proposal significantly improves the performance of the whole network, and meanwhile satisfies the QoS requirements of different applications.

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm2.

State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor

As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard to achieve low power consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits to make power gating more efficient with less static power. In this paper, we propose two novel state-retention flip-flop designs based on a parallel and series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can achieve state retention with zero static power. To demonstrate the application of these different designs, they are implemented in a 32-bit normally-off microprocessor with an energy break-even time of 1.47 µs for the parallel type design and 0.93 µs for the series type design, at a clock frequency of 15 MHz. We show that decreasing the power supply duty cycle to 0.9%, the average current of the processor core can be decreased by over 99% using either type of flip-flop.

A CASE FOR HYBRID INSTRUCTION ENCODING FOR REDUCING CODE SIZE IN EMBEDDED SYSTEM-ON-CHIPS BASED ON RISC PROCESSOR CORES

Embedded computing differs from general purpose computing in several aspects. In most embedded systems, size, cost and power consumption are more important than performance. In embedded System-on-Chips (SoC), memory is a scarce resource and it poses constraints on chip space, cost and power consumption. Whereas fixed instruction length feature of RISC architecture simplifies instruction decoding and pipeline implementation, its undesirable side effect is code size increase caused by large number of unused bits. Code size reduction minimizes memory size, chip space and power consumption all of which are significant for low power portable embedded systems. Though code size reduction has drawn the attention of architects and developers, the solutions currently used are more of cure than of prevention. Considering the huge number of embedded applications, there is a need for a dedicated processor optimized for low power and portable embedded systems. In the study, we propose a variation of Hybrid Instruction Encoding (HIE) for the embedded processors. Our scheme uses fixed number of multiple instruction lengths with provision for hybrid sizes for the offset and the immediate fields thereby reducing the number of unused bits. We simulated the HIE for the MIPS32 processors and measured code sizes of various embedded applications of MiBench and MediaBench benchmarks using an offline tool developed newly. We noticed up to 27% code reduction for large and medium sized embedded applications respectively. This results in reduction of on-chip memory capacity up to 1 mega bytes that is very significant for SoC based embedded applications. Considering the large market share of embedded systems, it is worth investing in a new architecture and development of dedicated HIE-RISC processor cores for portable embedded systems based on SoCs.

Design and implementation of 16 X 16 Truncated multiplier with different families of Xilinx

Multiplication and Squaring functions are widely used in many real time applications. They form an integral part in implementation of many Digital Signal Processing, Digital Image Processing and Multimedia algorithms. The size and power consumption of a DSP chip is influenced by the multiplication and squaring architectures that are used. The aim of this paper is to propose a novel fixed width, 16 bit parallel array multiplier. The proposed approach is aimed at providing a degree of flexibility to designers when it comes to designing fixed width multipliers with reduced area and delay. The design being proposed was implemented in Verilog, and simulation were carried out in Xilinx version 13.2.

Optimization of Power Consumption in VLSI Circuit

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.