Power Consumption Analysis Research Articles

Design and Performance Evaluation of Conventional 6T vs. Single-Ended 6T SRAM Cell

Abstract -As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

Comparative Analysis of Power Consumption and Resource Utilization in Open-Source and Proprietary Media Players while using Raw Videos

This study evaluates and compares the power consumption and resource utilization of open-source and proprietary media players during the playback of a large raw video file. Using real-time monitoring tools like HWiNFO, key metrics such as GPU power consumption, CPU power consumption, memory usage, and CPU usage percentage were collected and analyzed. The experiment was conducted on a system powered by a 12th Gen Intel(R) Core(TM) i7-12700H processor, and the media players were tested with a 2-minute, 14-second raw video file in .MOV format. A statistical analysis using t-tests was performed to assess the significance of the differences between the two categories. The results indicated that open-source media players generally exhibit lower GPU and CPU power consumption, with a potential for saving energy. Long-term power consumption analysis further demonstrated that users could achieve significant energy savings by opting for open-source media players, making them more suitable for energy-conscious environments. These findings highlight the trade-offs between power efficiency and performance while playing raw videos.

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

As open-source RISC-V cores continue to be released, the development of low-power multicore processors utilizing these cores is invigorating the edge/IoT device market. Nevertheless, comprehensive research on developing low-power multicore processors with integrated security features using existing open RISC-V cores remains limited. This study addresses this gap by introducing AESware, a dedicated lightweight hardware designed for energy-efficient AES (Advanced Encryption Standard) task execution, contributing to the development of AES-specific low-power RISC-V multicore processors. AESware supports variable key lengths and ensures minimal power consumption with a compact design. This standalone IP (Intellectual Property) is compatible with various open RISC-V cores, offering scalability and convenience. And importantly, we propose the most energy-efficient architecture for multicore processors equipped with AESware. Instead of assigning dedicated AESware to each core, we introduce a shared AESware architecture to maximize energy efficiency. We develop an operational algorithm for task scheduling in AESware, achieving maximum utilization and minimal latency while maintaining its lightweight nature. To evaluate our solution, we developed 24 processors into three groups: AESware-equipped, baseline, and those with an external AES accelerator per core. After FPGA (Field-Programmable Gate Array) prototyping for functional verification and power consumption analysis via 45 nm process technology synthesis, our findings revealed significant energy savings. AESware-equipped processors achieved up to 76%, 47%, and 33% energy savings at dual-, quad-, and octa-core configurations compared to baseline, respectively, and were more energy-efficient in running AES applications than those with individual accelerators.

Power-consumption analysis for different IPoWDM network architectures with ZR/ZR+ and long-haul muxponders

Operators are constantly faced with the need to increase optical-network capacity to accommodate rapid traffic growth while minimizing the cost-per-bit and power-per-bit. The drastic reduction of the power consumption of IP routers and ZR/ZR+ pluggable transponders seen in the past several years has renewed the interest in “opaque” optical-network architectures, where no optical bypassing is allowed. In this work, we aim to quantify and compare the power consumption of four “IP over wavelength division multiplexing” (IPoWDM) transport network architectures employing ZR/ZR+ modules versus long-haul muxponders, considering different grooming, regeneration, and optical bypassing capabilities. We first propose a power consumption model for different IPoWDM node architectures with ZR/ZR+ modules and long-haul muxponders. Then, to obtain the power consumption of different architectures, we propose a compact auxiliary-graph-based network-design algorithm extensible to different network architectures. Moreover, we investigate how the continuous decrease in the power consumption of ZR/ZR+ and IP routers can impact the power consumption of different architectures through a sensitivity analysis. Illustrative numerical results on networks of different sizes show that, despite drastic reductions of power consumption at the IP layer, optical bypassing is still the most power-efficient solution, reducing consumption by up to 48%.

Balancing Security and Efficiency: A Power Consumption Analysis of a Lightweight Block Cipher

This research paper presents a detailed analysis of a lightweight block cipher’s (LWBC) power consumption and security features, specifically designed for IoT applications. To accurately measure energy consumption during the execution of the LWBC algorithm, we utilised the Qoitech Otii Arc, a specialised tool for optimising energy usage. Our experimental setup involved using the Otii Arc as a power source for an Arduino NodeMCU V3, running the LWBC security algorithm. Our methodology focused on energy consumption analysis using the shunt resistor technique. Our findings reveal that the LWBC is highly efficient and provides an effective solution for energy-limited IoT devices. We also conducted a comparative analysis of the proposed cipher against established LWBCs, which demonstrated its superior performance in terms of energy consumption per bit. The proposed LWBC was evaluated based on various key dimensions such as power efficiency, key and block size, rounds, cipher architecture, gate area, ROM, latency, and throughput. The results of our analysis indicate that the proposed LWBC is a promising cryptographic solution for energy-conscious and resource-limited IoT applications.

A Comparative Study of CPU and GPU Power Consumption while using Open-Source and Proprietary Media Players

This study presents a comparative analysis of power consumption between open-source and proprietary media players when playing open-media format videos (.webm). As media consumption grows, energy-efficient software is critical for both environmental sustainability and device performance. Using tools like HWiNFO, key metrics such as GPU and CPU power consumption, memory usage, and efficiency were evaluated for popular open-source (e.g., VLC, Kodi) and proprietary (e.g., GOM Player, KMPlayer) players. The results reveal that open-source players generally consume less GPU power but more CPU resources, while proprietary players balance CPU and GPU usage with higher memory demands. The findings suggest that careful selection of media players can lead to significant energy savings over time, offering insights for developers and users focused on energy-efficient computing.

A Comparative Analysis of Power Consumption While Using Open-Source and Proprietary Media Players

This study investigates the power consumption of various media player software applications, comparing open-source and proprietary options. The experiment measured the average power consumption of CPU, GPU, and memory usage of media players such as Kodi, MPC, MPV, SMP, VLC, Windows Media Player, ACG, ALLPlayer, GOM, KMPlayer, LAPlayer, POTPlayer, and RealPlayer while playing 4K video. The results revealed that proprietary media players generally consume less power compared to their open-source counterparts. Statistical analysis, including descriptive statistics and independent samples t-tests, confirmed these findings. Long-term power consumption projections indicated substantial energy savings with more efficient media players. These findings underscore the importance of considering energy efficiency in software selection for sustainable computing.

A Comprehensive Review of Power Consumption in Digital Logic Circuits at Ultra-Low Subthreshold CMOS Levels

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

A Review on FPGA-based Architectures for Noise Removal of Digital Images using High-Level Design

Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture's visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De- noising).Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture's visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De- noising). Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

A Study on the Machinability and Environmental Effects of Milling AISI 5140 Steel in Sustainable Cutting Environments

AISI 5140 steel is an alloy frequently used in the manufacturing and automotive industries. This steel alloy is shaped using different manufacturing methods and cooling is required during this process. This research study included the milling of AISI 5140 steel utilizing various cutting settings and cooling/lubrication procedures. For this purpose, two cutting speeds (75–100 m/min), two feed rates (0.075–0.100 mm/rev), and four cooling media (dry, MQL, flood, nanofluid) were used. Then, 5% Mo nanoparticles were added to the nanofluid cutting fluid. Machinability and power consumption analyses were carried out using the input parameters selected in light of the manufacturer’s recommendations and studies in the literature. The effects of sustainable cutting fluids and their parameters on machinability and power consumption were investigated through experiments. This study concluded that the use of nanofluid led to improvements in surface roughness, flank wear, and power consumption characteristics. It was determined that the flood environment is the most effective in reducing the cutting temperature. As a result, it is predicted that nanofluid cutting fluids can be used during machining.

Optimization of guide plates and orifice plates on thermal management of battery energy storage system

The performance, state of health and lifetime of the battery energy storage system (BESS) depend heavily on the temperature uniformity between batteries. The BESS is more prone to uneven temperature distribution due to the inclusion of more battery modules. Improving the air supply uniformity of each battery module is the key to ensure the temperature uniformity of the system. In order to solve the problem of uneven air supply in traditional duct, the present study proposes a composite duct structure with optimized L-type guide plates and orifice plates. Based on the orthogonal analysis method, the optimization of guide plate structures in the sub duct and the main duct is completed. Combined with power consumption analysis, the porosity of orifice plates in the ducts is determined. The results show that when guide plates and orifice plates are in the best design condition, compared with the initial scheme, the air supply uniformity coefficient of the BESS is reduced from 75.07 % to 6.29 %. The air supply uniformity of the system is increased by 91.62 %. The maximum temperature difference of the BESS is reduced from 17.36 K to 4.35 K. The temperature uniformity of the system is increased by 74.94 %. This study is helpful to the design and optimization of the duct for the thermal management system of BESS in the future.

P‐54: XAI Models for Efficient Analysis of Temperature and Power Consumption in High‐Brightness Panels and Modules

Predicting temperature and power consumption in panels and modules under high brightness has long been a daunting and time‐intensive task, often requiring over a week of simulation work. Addressing this challenge, our study introduces a novel machine learning framework, bifurcated into panel and module stages, to streamline the data acquisition process. A key innovation in our approach is the use of symbolic regression to overcome the limitations posed by the reliance on real‐world measurements for power consumption and heat generation. Employing SPICE simulations, we estimated the current density within the panel, with subsequent validation through Explainable AI (XAI) analysis. This revealed a significant correlation between current density and panel heat generation. Our research also revisits the traditionally neglected areas outside the panel's center, uncovering their impact on heat generation. The layered complexity in modules, previously a barrier to physical sample creation and measurement, was navigated using simulation. XAI insights demonstrated the crucial roles of graphite and metal layers in heat dissipation, and the drive IC as a primary heat source. This integrated approach of real and computational data in machine learning significantly reduced the analysis timeframe from a week to mere minutes, marking a breakthrough in predictive accuracy and efficiency for high‐brightness scenarios.

Comparative performance evaluation of voltage gate-spin orbit torque MTJ-based digital logic circuits with 45 nm CMOS technology

The development of advanced logic systems relies on low-power, compact devices with incredibly fast computational speeds. Voltage gate spin–orbit Torque Magnetic Tunnel Junction has emerged as a prominent solution, meeting these requirements and playing a crucial role in the design of digital circuits. This paper concentrates on the design, implementation, and performance evaluation of gates (AND, OR, XOR) and combinational circuits (2 × 1 Mux, subtractor, and adder) based on VgSOT MTJ. The performance characteristics of these circuits have been evaluated, and comprehensive comparisons have been made with conventional 45 nm CMOS and SOT/STT-based circuit designs. In this paper, based on the latency performance analysis, it has been established that the logic gates and combinational circuits utilizing VgSOT exhibit superior performance of approximately 96% compared to CMOS counterparts. Similarly, latency performance improvement of 44% and 75%, respectively, is seen for VgSOT-based logic gates and combinational circuits over SOT and STT-based circuits. Analysis of power consumption in VgSOT-based logic gates has revealed a remarkable power efficiency of ∼98% over CMOS- and SOT/STT-based circuit implementations. Implementing VgSOT MTJ-based design brings about notable improvements in the performance of different logic designs.

Innovative claw rotor design for claw vacuum pump and its power consumption analysis

The claw vacuum pump is extensively utilized in semiconductor, photovoltaic and aerospace industries because of its dry oil-free and compact structure. In order to reduce the power consumption of the claw vacuum pump caused by its special mixing process during operation, a novel pair of claw rotors was proposed. This innovation involves replacing the conventional circular arc at the dedendum of the claw rotors with an eccentric circular arc. A geometric model of the novel claw rotor was established, and the geometric characteristics of both the novel and conventional claw rotors were compared. Subsequently, the optimal design parameters were determined. The pressure distribution and power consumption of two claw vacuum pumps were analyzed with numerical simulations. Study results indicates that the power consumption of the proposed claw vacuum pump in the mixing process is reduced by 72.3 %, and the total power consumption is reduced by 12.6 % compared to the conventional pump. The study is of great significance for reducing power consumption of the claw vacuum pumps and improving application.

Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder

The Newcomb-Benford law, also known as Benford's law, is the law of anomalous numbers stating that in many real-life numerical datasets, including physical and statistical ones, numbers have a small initial digit. Numbers irregularity observed in nature leads to the question, is the arithmetical-logical unit, responsible for performing calculations in computers, optimal? Are there other architectures, not as regular as commonly used Parallel Prefix Adders, that can perform better, especially when operating on the datasets that are not purely random, but irregular? In this article, structures of a propagate-generate tree are compared including regular and irregular configurations—various structures are examined: regular, irregular, with gray cells only, with both gray and black, and with higher valency cells. Performance is evaluated in terms of energy consumption. The evaluation was performed using the extended power model of static CMOS gates. The model is based on changes of vectors, naturally taking into account spatio-temporal correlations. The energy parameters of the designed cells were calculated on the basis of electrical (Spice) simulation. Designs and simulations were done in the Cadence environment and calculations of the power dissipation were performed in MATLAB. The results clearly show that there are PPA structures that perform much better for a specific type of numerical data. Negligent design can lead to an increase greater than two times of power consumption. The novel architectures of PPA described in this work might find practical applications in specialized adders dealing with numerical datasets, such as, for example, sine functions commonly used in digital signal processing.

Analysis of Power Consumption on BOP System in a Fuel Cell Electric Bus According to the Fuel Cell Load Range

The proton exchange membrane fuel cell (PEMFC) in a fuel cell electric bus (FCEB) converts hydrogen's chemical energy into electrical energy. The fuel cell system comprises a fuel cell stack and a balance of plant (BOP) system, which efficiently controls the stack. Fuel cell and battery are sensitive to operational temperature, which directly impacts performance, lifespan, and safety. Therefore, a thermal management system (TMS) is necessary to maintain an appropriate temperature by dissipating the heat generated by the fuel cell and battery. In this study, the exponential or quadratic relationships between the power consumption of the major components of an FCEB and various factors, such as temperature and flow rate influencing the operational behavior and control of the components, were analyzed based on the results of a dynamometer vehicle test. Additionally, the vehicle's energy flow was calculated under different fuel cell load conditions. When the fuel cell operated at 56.3 kW, TMS power was 6.6 times higher than at 20 kW. At full load, under 90 kW, it increased to 17.4 times higher. The rise in fuel cell load correlated with higher heat generation, resulting in a significant increase in power consumption for both the radiator fan and coolant pump.

PID Temperature Control of Baby Incubator Transport Battery Efficiency

Transport baby incubators are used to keep babies warm and safe while in transport using battery voltage sources or DC electricity, which are portable and can be used without getting a supply of electrical energy. The problem that often occurs with this tool is the limited battery power system. causes a risk to the infant in the event of power failure or battery exhaustion. We aim to evaluate the battery efficiency of Baby Incubator Transport using a PID temperature controller. The evaluation is done by comparing and analyzing the battery voltage of the device to the standard device, as well as considering the setting temperature and duration of use of the device so that it can provide convenience in evacuating babies in an emergency. The tool uses the PID method to control temperature and maximize battery power. In this design, researchers only look at the efficiency of the PID method on temperature control and the battery to be used. This module will have a display that will display the battery voltage value, battery voltage percentage, skin temperature, chamber temperature, humidity, and temperature control that has been selected in the form of a graph. Compared with the digital multimeter measuring instrument. From the results of data collection, it can be concluded that the PID method has a faster rise time to reach the setting temperature, while the fuzzy method has a longer rise time to reach the setting temperature. However, the PID method requires more battery power than the Fuzzy method. The measurement results between the display and the measuring device have a difference of 3.1% at 34°C, at 35°C it is 3.9%, and at 36°C it is 4.7%. The biggest error is at a temperature of 36ºC, the smallest is at a temperature of 34ºC. Based on the results of the observation analysis of battery power consumption, it is found that the smaller the battery energy, the smaller the current issued, as well as the voltage issued. But if the load is large, the current is inversely proportional to the center, the battery voltage decreases while the current increases.

Enhancing Embedded Object Tracking: A Hardware Acceleration Approach for Real-Time Predictability.

While Siamese object tracking has witnessed significant advancements, its hard real-time behaviour on embedded devices remains inadequately addressed. In many application cases, an embedded implementation should not only have a minimal execution latency, but this latency should ideally also have zero variance, i.e., be predictable. This study aims to address this issue by meticulously analysing real-time predictability across different components of a deep-learning-based video object tracking system. Our detailed experiments not only indicate the superiority of Field-Programmable Gate Array (FPGA) implementations in terms of hard real-time behaviour but also unveil important time predictability bottlenecks. We introduce dedicated hardware accelerators for key processes, focusing on depth-wise cross-correlation and padding operations, utilizing high-level synthesis (HLS). Implemented on a KV260 board, our enhanced tracker exhibits not only a speed up, with a factor of 6.6, in mean execution time but also significant improvements in hard real-time predictability by yielding 11 times less latency variation as compared to our baseline. A subsequent analysis of power consumption reveals our approach's contribution to enhanced power efficiency. These advancements underscore the crucial role of hardware acceleration in realizing time-predictable object tracking on embedded systems, setting new standards for future hardware-software co-design endeavours in this domain.

Power Consumption Analysis of a Prototype Lightweight Autonomous Electric Cargo Robot in Agricultural Field Operation Scenarios

The continuous growth of the urban electric vehicles market and the rapid progress of the electronics industry create positive prospects towards fostering the development of autonomous robotic solutions for covering critical production sectors. Agriculture can be seen as such, as its digital transformation is a promising necessity for protecting the environment, and for tackling the degradation of natural resources and increasing nutritional needs of the population on Earth. Many studies focus on the potential of agricultural robotic vehicles to perform operations of increased intelligence. In parallel, the study of the activity footprint of these vehicles can be the basis for supervising, detecting the malfunctions, scaling up, modeling, or optimizing the related operations. In this regard, this work, employing a prototype lightweight autonomous electric cargo vehicle, outlines a simple and cost-effective mechanism for a detailed robot’s power consumption logging. This process is conducted at a fine time granularity, allowing for detailed tracking. The study also discusses the robot’s energy performance across various typical agricultural field operation scenarios. In addition, a comparative analysis has been conducted to evaluate the performance of two different types of batteries for powering the robot for all the operation scenarios. Even non-expert users can conduct the field operation experiments, while directions are provided for the potential use of the data being collected. Given the linear relationship between the size and the consumption of electric robotic vehicles, the energy performance of the prototype agricultural cargo robot can serve as a basis for various studies in the area.

Cognitive Modelling and Forecasting of Electricity Consumption

Purpose of reseach. Development of a forecast model of energy consumption and assessment of factors influencing its consumption. The obtained forecast estimates of energy consumption will improve the quality and efficiency of management decisions at all levels of administrative management.Methods. The article presents an analytical review of the existing methods of cognitive modelling and forecasting of electric power consumption, the description of the software implementation of the information-computing system that allows to make a forecast of electric power consumption by the population of the administrative-territorial formation. The approach to the description of factors of electric power consumption by both population and various branches of national economy, as well as organisations engaged in rendering various services has been proposed. Special software has been developed, which allows to obtain model results of electric power consumption in an automated mode, to carry out factor analysis of power consumption. The experimental verification of the work of the programme of cognitive modelling and forecasting of electric power consumption by the population of Lgovsky district of Kursk region is given. The developed software also makes it possible to evaluate the adequacy of the obtained results and promptly adjust the model parameters.Results. As a result of the research a fuzzy cognitive map of energy consumption for a municipal entity was developed. The concepts of the subject area describing the influence of various groups of factors on the level of electric energy consumption were identified. Forecast estimates of electricity consumption were obtained, which were based on the data for the retrospective period. Adequacy indicators based on the calculation of statistical criteria are determined for the obtained estimates.Conclusion. The results of the study have shown that the combination of cognitive and statistical methods allows to achieve an adequate solution when solving the problem of energy consumption forecasting.