Power Back-off Research Articles

A Ka-Band Doherty Power Amplifier in a 150 nm GaN-on-SiC Technology for 5G Applications

This paper presents a Ka-band three-stage power amplifier for 5G communications, which has been implemented in a 150 nm GaN-on-SiC technology and adopts a Doherty architecture. The amplifier is made up of a 50 Ω input buffer, which drives a power splitter, thanks to which it delivers its output power to the two power amplifier units of the Doherty topology, namely the main and auxiliary amplifier. Finally, the outputs of the two power amplifiers are properly arranged in a current combining scheme that enables the typical load modulation of the Doherty architecture, alongside allowing power combining at the final output. The proposed amplifier achieves a small signal gain of around 30 dB at 27 GHz, while providing a saturated output power of 32 dBm, with a power-added efficiency (PAE) as high as 26% and 18% at peak and 6 dB output power back-off, respectively.

A Highly-Efficient Doherty Power Amplifier With Generalized Parallel-Circuit Class-EF Mode

In this letter, a highly-efficient Doherty power amplifier (DPA) architecture with generalized parallel-circuit class-EF mode is proposed. With this topology, the ideal harmonic impedance conditions at the deep power back-off (PBO) region and saturation region can remain the same. Based on it, by adding a single harmonic control network (HCN) and an offset line, the carrier PA can be operated at the ideal high-efficiency conditions within the above two regions. In this case, the overall efficiency of the DPA can be improved simultaneously. As an example, a high-efficiency DPA working at 2.6 GHz is designed and fabricated based on a Wolfspeed CGH40010F GaN HEMT transistor. The measured results of the proposed structure demonstrated that a drain efficiency (DE) of 76.7% with the peak outpower of 45.2 dBm, as well as DE of 74.8 % at the 6dB power back off region.

Broadband Asymmetric GaAs MMIC Doherty Power Amplifiers With Simplified Peaking Matching Network and Output Capacitance Compensation

This letter proposes a compact asymmetric Doherty power amplifier (DPA) structure with a simplified peaking matching network (MN), and the output capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm{OUT}})$</tex-math> </inline-formula> of the peaking transistor is considered under different power states. The load–pull, including the MNs of carrier and peaking branch, is taken place to demonstrate the suggested scheme. For verification, a monolithic microwave integrated circuit (MMIC) DPA was designed and manufactured using a 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m GaAs process. The measurement results show that over a wideband of 4.3–6.0 GHz, the saturated output power is 29.4–30.4 dBm with a drain efficiency (DE) of 46.4%–57.1%. At 9-dB power back-off (PBO), the DE is 31%–43%.

Dual-Band Dual-Output Doherty Power Amplifier for Unsynchronized Time-Division Duplexing

Conventional multiband power amplifiers (PAs), when working in time-division duplex (TDD), require the transmit–receive intervals of all bands to be synchronized. This is an undesirable constraint in modern radio base stations. This article proposes a dual-output dual-band Doherty PA (DB-DPA) that enables the loading of one band to be switched on-and-off without impacting the other band in normal transmission. A thorough analysis of the proposed dual-output DB-DPA architecture is presented, and a dual-output DB-DPA prototype operating at 1.4 and 2.6GHz has been designed as a proof of concept. The large-signal measurements of the prototype DB-DPA indicate Doherty behavior at both frequencies with over 56% saturation efficiency and 45% efficiency at 6-dB power back-off (PBO). Furthermore, single-band and concurrent dual-band linearized modulated measurements, using 10-MHz new radio (NR) signals with 6-dB peak-to-average power ratio (PAPR), demonstrate the linearizability of the proposed DB-DPA and its usefulness for unsynchronized TDD applications.

Application of Load-Pull X-Parameters for GaN Device-Based Load Modulated Balanced Power Amplifier Design

In this work, the design of a load modulated balanced power amplifier (LMBA), which composed of a pair of classical balanced power amplifier (BA) and a signal control power amplifier (CA), based on using the X-parameter model is presented for the first time. A 10-W gallium nitride (GaN) packaged transistor is used for the power amplifier (PA) design. The extracted X-parameter model of the device under test (DUT) can accurately predict the nonlinear behavioral of the device, including both fundamental and harmonic characteristics, and determine the region of the Smith chart that leads to the optimal output power and drain efficiency (DE), with which the BA and CA are designed. In order to facilitate the application of the X-parameter for LMBA design, the X-parameter model of the classical BA pair is further extracted. Finally, an LMBA is fabricated and tested to verify the validity of the proposed design methodology. The measurements performed on the developed prototype show a saturation output power of up to 43.2 dBm in the frequency range of 1.3 GHz-1.6 GHz, with a saturation DE over 73% and an output power back-off (OBO) efficiency over 51% when it has more than 9 dB output power back-off. A single-carrier 20-MHz long-term evolution (LTE) signal is used to test the designed PA, and performance of the amplifier both with and without linearization are given.

Compact Asymmetrical Quasi-MMIC Doherty Power Amplifier

This paper presents a compact asymmetrical Doherty power amplifier (PA) based on a quasi-MMIC configuration for 5G sub-6 GHz applications. The proposed Doherty PA is composed of commercial GaN HEMTs and several passive components implemented on a silicon (Si) substrate. In order to achieve size and cost advantages, passive components such as a power divider, input matching networks, output matching networks, and a Doherty combiner are realized using Si-integrated passive device (Si-IPD) technology, which costs about 40% of the budget for the entire GaN MMIC process. For the 3.5 GHz pulsed-continuous waveform signal, the fabricated Doherty PA has an efficiency of 52.6% at a saturated output power of 44.2 dBm. Furthermore, an efficiency of 45.6% was achieved with the output power back-off (OBO) of 7.0 dB. The implemented PA occupies only 8.9 mm × 5.6 mm.

A Dual Load-Modulated Doherty Power Amplifier Design Method for Improving Power Back-Off Efficiency.

In this paper, the load modulation process of a Doherty power amplifier (DPA) is analyzed to address the issue of why designed DPAs have a very low efficiency in the back-off state in some cases. A general formula of the real load modulation process is also given for analyzing the load modulation of a peak PA matching network. This provides a new perspective for improving the back-off efficiency of a DPA. To improve the power back-off efficiency of a DPA, a dual load-modulated DPA (D-DPA) design method is proposed. The core principle of the proposed design method is to control the load modulation process from the carrier PA to the peaking PA based on the design method of the traditional two-way DPA. The efficiency of the peaking PA in the back-off region is enhanced, thereby improving the efficiency in the entire back-off region of the DPA. Based on the proposed design method, a D-DPA operating at 2 GHz is designed and fabricated. The test results show that the saturated output power and gain are 43.7 dBm and 9.7 dB, respectively, while the efficiency at 6 dB output power back-off is 59.2%. The designed D-DPA eliminates the efficiency pit of the traditional two-way DPA in the output power back-off region.

A 28-GHz 26.8-dBm Doherty Power Amplifier With Four-Way Differential Hybrid Load- Modulated Combiner in 55-nm CMOS

This letter presents a 28-GHz high-power four-way differential Doherty power amplifier (PA) in 55-nm bulk CMOS technology. A transformer-based hybrid load-modulated combiner (HLMC) (i.e., a parallel combined series-load-modulated Doherty output network) is proposed to simultaneously achieve high output power, low-loss power combining, and a true-Doherty load modulation. Meanwhile, the closed-form expressions of the proposed combiner are derived. The measured results of the proposed Doherty PA demonstrate a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{sat}}$</tex-math> </inline-formula> of 26.8 dBm, an output 1-dB compression point (OP1dB) of 25.2 dBm, a peak power added efficiency (PAE) of 26.7%, and 19.2% PAE at 6-dB power back-off (PBO) at 28 GHz. The PA is also tested with 400-MSym/s 64-quadrature amplitude modulation (QAM) signals, and it achieves 17.9-dBm average output power with 14.1% average PAE at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 26.2-dB error vector magnitude (EVM).

TCAD assisted design of the Doherty Power Amplifier

Nonlinear physics-based TCAD simulations based on the Harmonic Balance technique represent an important tool to link the performance of microwave circuits to the active device fabrication technology (Donati Guerrieri et al., 2016 [1,2]). While nonlinear TCAD simulations were previously limited to the analysis of circuits including a single device, starting from Donati Guerrieri et al. (2022) they have been extended to circuits with multiple interacting devices. This work, further extending Donati Guerrieri et al. (2022), shows a complete example of the design of a Doherty Power Amplifier fully assisted by TCAD nonlinear simulations. The analysis allows for a complete inspection of the internal physical variables of the DPA, including carrier concentrations and electrostatic potential, making it possible to verify the correct operation of the main and auxiliary devices. The proposed DPA, exploiting a GaAs MESFET technology, achieves 30 dBm output power at 12 GHz with peak Power Added Efficiency (PAE) of 52% at 6 dB Output Power Back-off (OBO) and 5 dB gain. The reported results show that the power split ratio between the MAIN and AUX amplifier can be used to achieve a good compromise between linearity and efficiency.

Compact 40% Fractional Bandwidth Doherty PA With Input Group Delay Engineering

This letter presents a wideband Doherty power amplifier (DPA) design based on the control of the relative input group delay between the carrier and peaking amplifiers. By reaching an appropriate input phase variation over the target bandwidth, frequency dispersion of load modulation is minimized and a less dispersive DPA at peak power is achieved. To validate this approach, a compact DPA with 50-dBm peak power is developed and shows 51%–57% drain efficiency at 8-dB output power back-off (OBO) with a small-signal gain of 14.4–17 dB over 1.8–2.7 GHz which represents 40% fractional bandwidth (FBW). Linearization of the prototype is proven using DPD correction with ACPR below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 60 dBc measured in single-band scenarios. Moreover, under 400 MHz of instantaneous bandwidth, the proposed DPA achieves ACPR below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 53 dBc with an average efficiency of 48%.

Design of a Load Modulated Balanced Amplifier with a Two-Stage Control Power Amplifier

While an ideal Doherty power amplifier has a linear response, the load modulated balanced amplifier (LMBA) has a compressive response under ideal conditions. This inherent nonlinear characteristic is due to the lower power contribution of the single auxiliary device as the balanced amplifier transistors approach compression. This article presents an LMBA with a two-stage control signal amplifier in place of the single auxiliary device. The idea is to preserve a high and constant gain across the high- and low-power regions by tuning the two-stage gain control signal to match the balanced amplifier gain. An optimal load trajectory can be found for a high-efficiency design by appropriately terminating the second harmonic while ensuring an optimal impedance match in all devices. At the same time, by setting an optimal output power from the auxiliary device, sufficient power is provided to linearize the response of the main power amplifier beyond the output back-off power boundary. As proof of concept, a prototype is designed and implemented. The experimental measurements demonstrate a drain efficiency of 59%–64% at maximum output power and 46%–52% at 7.5 dB output back-off power over the target frequency range of 3.3–3.8 GHz.

Analysis of Doherty Power Amplifier Matching Assisted by Physics-Based Device Modelling

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from class AB to class C. For the class C case, library models are often inaccurate, while experimental characterization is difficult since it must be carried out in large signal conditions and with varying gate bias. In this paper, we propose an alternative approach, based on physics-based Technological CAD (TCAD) simulations of the complete Doherty amplifier along with the analysis of its individual MAIN (class AB) and AUXILIARY (class C) stages. TCAD simulations seamlessly provide an accurate modelling of the device behavior in all operation classes, including the device turn-on and the nonlinear capacitances, and easily account for the cross-loading effects of the MAIN and AUXILIARY devices through the output network and the effect of the device feedback (gate-drain) capacitance on the input matching. Analyzing a GaAs Doherty stage at 12 GHz, we show that the input phase of the auxiliary stage can be exploited for the Doherty power amplifier optimization in terms of gain, linearity and efficiency, showing a 9 dB gain with less than 1 dB gain variation from back-off to peak power with a power-added efficiency exceeding 45% over a Doherty region extending to a more than 6 dB output power back-off.

Broadband Sequential Load Modulated Balanced Amplifier With Extended Design Space Using Second Harmonic Manipulation

This article presents the design methodology of a broadband radio frequency (RF)-input sequential load modulated balanced amplifier (SLMBA) with extended high-efficiency design space, by introducing the second-harmonic load manipulation over an enlarged range for the control amplifier (CA). The extension of CA load design space not only can provide the time-domain-varying drain current waveform inside the entire design continuum but also allows maintaining high efficiency at output power back-off (OBO) over an extended operation bandwidth. To validate the theory, a broadband SLMBA operating at 2.05–3.65 GHz was designed and fabricated using packaged gallium nitride (GaN) transistors. The implemented power amplifier (PA) attains a measured 45.2–46.8-dBm peak output power. Drain efficiency (DE) of 61.2%–79.7% at saturation and 50.5%–66.2% at 8-dB OBO is achieved throughout the designed bandwidth. When tested with a 100-MHz long-term evolution (LTE) signal with a peak-to-average-power ratio (PAPR) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8$</tex-math> </inline-formula> dB, the proposed SLMBA achieves 50.7%–63.5% average DE over 2.05–3.55 GHz and better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 45.1 dBc adjacent channel power ratio (ACPR) after digital predistortion (DPD).

A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station

This article demonstrates a 39-GHz CMOS phased-array beamformer aiming for power-efficient and area-efficient fifth-generation (5G) dual-polarized multiple-in–multiple-out (DP-MIMO) applications. To address the digital pre-distortion (DPD) implementation issue in the massive beamformer elements with Doherty technique integrated, an inter-element mismatch compensation technique is introduced for improving the shared-lookup table (LUT) DPD performance over the process, voltage and temperature (PVT) variations. A bidirectional Doherty power amplifier (PA)-LNA is proposed to enhance the power back-off (PBO) efficiency regarding the high peak-to-average power ratio (PAPR) 5G signals, meanwhile cost down the system by the unbalanced neutralized bidirectional operation. The proposed phased-array beamformer chip is fabricated in 65-nm CMOS technology and packaged in a wafer-level chip-scale package (WLCSP). Each element occupies only a 0.82-mm2 chip area, including the on-chip low-dropout regulator (LDO). The measured stand-alone Doherty PA-LNA achieves 18.9-dBm saturated output power with 17.8% power-added efficiency (PAE) at 6-dB PBO in PA mode and obtains a 4.8-dB noise figure (NF) at 40 GHz in LNA mode. By utilizing the proposed mismatch compensation, the measured 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiple access (OFDMA)-mode error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) with the shared-LUT DPD are improved from −22.4 to −25.0 dB and from −28.7 to −32.1 dBc, respectively. The 64-element module achieves a 55.2-dBm saturated effective isotropic radiated power (EIRP) and supports 21-Gb/s single-carrier (SC) mode data streaming. The measured 64-element transmitter (TX) EVM is −25.2 dB at 43.2 dBm with 3.5-GSymbol/s baud rate in 64 QAM, and the corresponding 64-to-4 elements TX-to-receiver (RX) EVM is −22.5 dB. The consumed power for each element is 402 mW at saturation output point in TX mode and 87 mW in RX mode.

A Coupler Balun Load-Modulated Power Amplifier With Extremely Wide Bandwidth

Next-generation millimeter-wave (mm-Wave) power amplifiers (PAs) need to support multistandard communication systems with wide bandwidth, complex modulation, and high energy efficiency. Most existing mm-Wave PA architectures with power backoff (PBO) efficiency enhancement, such as Doherty and outphasing PAs, typically only support limited carrier bandwidth. In this work, we propose and demonstrate that a 180° coupler balun structure can serve as an extremely wideband active load modulation network for broadband PBO efficiency enhancement and further realize a coupler balun load-modulated PA (CBMA). Moreover, compared to load-modulated balanced amplifiers (LMBAs), the proposed CBMA supports natural single-ended-to-differential balun conversion, differential power cells, and wideband capacitive neutralization, ideal for integrated mm-Wave PAs. Furthermore, we propose a continuous-mode CBMA operation with role exchanges to attain a nearly 3:1 carrier bandwidth. A prototype CBMA is designed and fabricated in a 45-nm RF CMOS SOI process, which achieves an OP1 dB PAE of 39.9%–20.4% with OP1 dB of over 21.6–18.3 dBm from 26 to 60 GHz. The PA also achieves a 32.8%–13.4% 6-dB PBO (from OP1 dB) efficiency with its best <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.75\times /3.51\times $ </tex-math></inline-formula> efficiency enhancement over an ideal Class-B/-A PA. Using a single-carrier 64-QAM signal with 0.5 GSym/s (3 Gb/s), the PA supports an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {out}}$ </tex-math></inline-formula> of 15.8–11.3 dBm with an average PAE of 27.15%–8.58% with −23-dB rms error vector magnitude (EVM) over 26–60 GHz. The PA also supports 5G NR modulation using 5G new radio (NR) FR2 200-MHz 1-CC 64-QAM signals, achieving 18.22%–6.55% average PAE at 10.72–7.1-dBm average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {out}}$ </tex-math></inline-formula> with rms EVM of −23 dB over 26–60 GHz.

A Broadband Analog Predistortion Linearizer Based on GaAs MMIC for Ka-Band TWTAs

In this article, a Ka-band broadband analog predistortion (APD) microwave monolithic integrated circuit (MMIC) with independent tunability based on a 0.15 μm GaAs pHEMT process is proposed, which can be cascaded in front of traveling wave tube amplifiers (TWTAs) to improve their linearity. The influence of different diode sizes on the parameters of Schottky diodes is analyzed and used to design the gain and phase nonlinear branches. The broadband APD MMIC is realized based on a dual-branch vector synthesis design and nonlinear frequency adjust module (NFAM). The independent tunability and broadband characteristics of the APD MMIC are verified by simulated and measured results with an error of less than 5%. Furthermore, a Ka-band 60 W TWTA is linearized by the APD MMIC, and the gain and phase compressions are reduced from 8 dB and 50° to within 3 dB and 12°, respectively. The third-order intermodulation (C/IM3) is greater than 28 dBc and noise power ratio (NPR) is greater than 15.7 dBc at 3 dB output power backoff (OPBO) over the operating band of 25.1~27.5 GHz, indicating that the APD MMIC can improve the nonlinearity of TWTA effectively under broadband signals.

A 41-GHz 19.4-dBm P&lt;sub&gt;sat&lt;/sub&gt; CMOS Doherty power amplifier for 5G NR applications

In this letter, a 41-GHz Doherty power amplifier (PA) in standard 65nm CMOS technology is introduced for 5G New Radio (NR) applications. The proposed PA implements the transformer-based parallel-combined Doherty structure to enhance the power-added efficiency (PAE). A tunable 90-deg hybrid coupler is proposed for output phase compensation. This work achieves a saturated output power (Psat) of 19.4dBm and an OP1dB of 18.6dBm at 41.5GHz under a 1-V power supply. The peak PAE and the PAE at 6-dB output power back-off (PBO) are 30.4% and 19.2%, respectively. This work also supports single-carrier mode (SC-mode) 400-MSymbols/s 256QAM and OFDMA-mode 400-MHz 256QAM. The core chip area is 0.22 mm2 with a static power consumption of 76mW.

Mitigating Clipping Distortion in Multicarrier Transmissions Using Tensor-Train Deep Neural Networks

Multicarrier transmissions, such as orthogonal frequency/chirp division multiplexing (OF/CDM), offer high spectral efficiency and low complexity equalization in multipath fading channels at the cost of high peak-to-average power ratio (PAPR). High peak powers can occur randomly and may drive the power amplifier (PA) into saturation, resulting in non-linear distortion. In this work, we propose a novel tensor-train (TT) deep neural network (DNN) architecture combined with soft clipping to reduce the PAPR to a deterministic level and minimize in-band distortion, while also satisfying spectral mask constraints. The proposed solution requires modifications only at the transmitter and there is no loss of spectral efficiency. Employing the TT decomposition allows for significant reduction in parameters. Results show that the proposed solution allows for significant reduction in PAPR with minimal performance loss. Furthermore, an upper bound for the PAPR is also derived which allows for the prediction of the required input power back off (IBO) without extensive simulations and trial-and-error.

Broadband Doherty Power Amplifier Using Short Ended λ/4 Transmission Lines Based on the Analysis of Negative Characteristic Impedance

This paper presents a broadband Doherty power amplifier (DPA) using quarter-wavelength ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4) transmission lines with negative characteristic impedance. In conventional DPA designs, the load modulation network is frequency-dependent, leading to bandwidth limitation at the back-off power region. In this design, by integrating two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4 transmission lines with negative characteristic impedance into the main and auxiliary branches, the impedance at the back-off power can be manipulated to maintain high efficiency at back-off power over a wide frequency range. Thus, the operational bandwidth is extended. In circuit realization, the two negative characteristic impedance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4 transmission lines are replaced by paralleled negative LC components. Then, the negative capacitor is combined into the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pi $ </tex-math></inline-formula> -shaped impedance matching network, while the negative inductor is eliminated by introducing Norton transformation. For verification, a broadband DPA with a fractional bandwidth of 108.6% from 0.8 to 2.7 GHz is implemented. The measured saturated output power is 41.8-44 dBm. The saturated and 6-dB back-off power drain efficiencies are 47.6%-84.4% and 39.5%- 52%, respectively. A 20-MHz LTE modulated signal with peak-to- average power ratio (PAPR) of 7.5 dB is also applied to measure the fabricated DPA. After digital predistortion, the adjacent channel leakage ratio (ACLR) better than −45.35 dBc is achieved, and the measured average efficiency is higher than 40% within the operating band.

A Ka-Band Watt-Level High-Efficiency Doherty Amplifier MMIC in 90-nm GaAs Technology

This letter presents a Ka-band watt-level high-efficiency Doherty power amplifier (DPA) monolithic microwave integrated circuit (MMIC) in 90-nm gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) technology. To realize the high efficiency of DPA at 6-dB power back-off (PBO), a low-loss compact Doherty output network is proposed to directly combine the matching network and the load modulation network (LMN) into a compact network. Then, the peaking amplifier of DPA is an optimized design to guarantee a sufficient load modulation at the 6-dB PBO level. The proposed DPA exhibits a measured saturation output power in the range of 29.5–30 dBm, with a corresponding peak power-added efficiency (PAE) in the range of 35%–40% from 26.5 to 30.5 GHz. Moreover, the PAE at the 6-dB PBO level of the proposed DPA is in the range of 25%–30.2% from 26.5 to 30.5 GHz.