Abstract
In this letter, a highly-efficient Doherty power amplifier (DPA) architecture with generalized parallel-circuit class-EF mode is proposed. With this topology, the ideal harmonic impedance conditions at the deep power back-off (PBO) region and saturation region can remain the same. Based on it, by adding a single harmonic control network (HCN) and an offset line, the carrier PA can be operated at the ideal high-efficiency conditions within the above two regions. In this case, the overall efficiency of the DPA can be improved simultaneously. As an example, a high-efficiency DPA working at 2.6 GHz is designed and fabricated based on a Wolfspeed CGH40010F GaN HEMT transistor. The measured results of the proposed structure demonstrated that a drain efficiency (DE) of 76.7% with the peak outpower of 45.2 dBm, as well as DE of 74.8 % at the 6dB power back off region.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
