Abstract
Enhancing PA efficiency in the power back-off (PBO) region has become an important design objective due to the high peak-to-average power-ratio (PAPR) modulation in modern communications. Recently, a voltage-mode subharmonic switching (SHS) digital PA architecture has been reported in [1] –[3]. The concept of SHS is to toggle a PA cell at a subharmonic frequency for more efficient PBO operation. However, the dynamic power loss of voltage-mode PAs (e.g., Class-D PAs) increases linearly with the operating frequency [4]. On the other hand, current-mode digital PAs are more suitable for higher carrier frequencies due to their zero-voltage-switching (ZVS) operation to reduce dynamic loss. However, the existing current-mode PA architecture still suffers from poor impedance matching at PBO and conduction loss of the driver, leading to distortion and PBO efficiency degradation. To alleviate those drawbacks, we propose a current-mode SHS PA architecture to reduce conduction loss and minimize output impedance variation, simply by toggling more PA branches at subharmonic frequencies in the PBO region. At the circuit level, we propose a coupled-inductor-based subharmonic trap to achieve the following: 1) derive the optimal load impedance at the carrier frequency (Fc) and high impedance at the subharmonic frequency (Fc/3), 2) reduce the inductor area, 3) achieve common-mode rejection via magnetic field cancellation, 4) avoid voltage reverse biasing of the PA drivers for better reliability, and 5) provide additional attenuation of the subharmonic component caused by the mismatch of phase interleaving [5]. The proof-of-concept prototype achieves 27dBm peak output power at 5.7GHz and 40.1% drain efficiency at 5.4GHz. Due to the current-mode SHS operation, the efficiency peak at -9dB PBO is 29.2% at 5.4GHz, which is a 2× improvement over that of the conventional current-mode digital PA. The real-time SHS operation achieves more than 28% average efficiency with 20/40/80MHz modulation signals.
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