4.1 A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency

Abstract

Modern wireless communication systems often utilize spectrum-efficient modulation schemes for higher data throughput, given the finite bandwidth. This type of modulation schemes, such as Orthogonal Frequency Division Multiplexing (OFDM), results in a high peak-to-average power ratio (PAPR) for the transmitted signal. Therefore, power amplifier efficiency in the power back-off (PBO) region has become an important design target. Meanwhile, obtaining high output power and high average efficiency still remains a key design challenge when developing an integrated CMOS PA. Recently, a subharmonic switching (SHS) digital PA architecture was reported in [1]. It toggles the PA cell at the subharmonic component of the carrier frequency (Fc) to achieve power back-off. The slower toggling rate reduces dynamic and conduction loss in the switching PA, resulting in better PBO efficiency. However, the SHS PA requires additional notch filtering of the subharmonic components in the matching network. Therefore, we propose a phase-interleaved architecture that combines three SHS PAs to increase output power (Watt-level) and inherently cancel the subharmonic components in the PBO mode, thereby alleviating the burden of the matching network. Moreover, multiple subharmonic components are utilized to create a greater number of efficiency peaks in the PBO region. This is referred to as a multi-SHS scheme. Lastly, a hybrid Class-G operation, in combination with the multi-SHS scheme, is used to further enhance average efficiency.