Power Amplifier Prototype Research Articles

A broadband GaN HEMT power amplifier based on feeding capacitance compensation method

In order to better cover the frequency band of fifth-generation communication system in sub-6GHz frequency, a feeding capacitance compensation method is proposed to improve the bandwidth and efficiency of power amplifier (PA). By adding different feeding capacitance at the drain supply voltage network, resonance valley points occurred at different frequencies are compensated to achieve wide bandwidth and high-efficiency. For validation purpose, a PA prototype is designed with using a 10-W Cree GaN high electron mobility transistor device. Maximum 64.7% efficiency has been measured over 80% bandwidth from 2.2 to 5.1 GHz, with maximum output power of 13.5 W. The measurement revealed an adjacent channel leakage ratio of better than −50.3 dBc after digital pre-distortion while being driven with a 40-MHz orthogonal frequency-division multiplexing modulated signal with a peak-to-average power ratio of 6.5 dB at an average output power of 32.5 dBm.

Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation

In this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors' transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25-μm GaN-on-SiC process with 28-V supply, provides 35.1-38.9dBm output power, 45-61% drain efficiency (DE), 40-55% power-added efficiency (PAE), and 11.3-13.4dB power gain, across 2.0-4.0GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4GHz, it achieves 2.5% (-32.0dB) rms error vector magnitude (EVMrms) and -37.5/-37.6dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1dBm and 20.6/19.5%, without predistortion. EVMrms and ACLR can be improved to 0.5% (-46dB) and -46.4/-46.8dBc by using digital predistortion (DPD).

One-Chip Integration of RF MEMS Switched Capacitor and Power Amplifier Using CMOS-Compatible Post Fabrication Process

This study presents a single-chip integrated reconfigurable 180-nm complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a radio frequency micro-electro-mechanical system (RF MEMS) switched capacitor, which is highly useful for advanced wireless mobile communication systems. The proposed reconfigurable PA prototype was designed to support the 0.9, 1.8, 2.4, and 5.0 GHz quad-bands by varying the capacitance values of the RF MEMS switched capacitor at the output matching network. The RF MEMS switched capacitor was post-fabricated on the same silicon substrate with which the PA circuit was integrated using 180-nm CMOS fabrication technology. The entire fabrication step was performed based on a CMOS-compatible low-temperature post process to avoid the performance degradation of the CMOS PA circuit. The fabricated RF MEMS switched capacitor exhibited capacitances of approximately 1.0 and 3.9 pF at a frequency of 0.9 GHz in its OFF and ON states, respectively. The measured output powers of the integrated quad-band PA were 27.13, 26.63, 26.29, and 23.43 dBm at the frequencies of 0.9, 1.8, 2.4, and 5.0 GHz with the continuous-wave signal, respectively.

A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters

We present a broadband dual-channel power amplifier (PA) with crosstalk suppression for multi-input multi-output (MIMO) communications. Operation of MIMO system with crosstalk is theoretically evaluated for two popular coding schemes including the space-time coding and linear precoding. Design challenges of a multi-channel PA on a single chip are investigated and circuit techniques, including second-harmonic trapping integrated into the output matching network and the use of back-via lines to isolate the channels, are proposed to mitigate the inter-channel crosstalk. A fully integrated dual-channel PA prototype, implemented using a 250-nm GaN-on-SiC process, provides 34.9–36.3dBm output power, 44–49% power-added efficiency (PAE), 11.3–12.3 dB power gain, 31.0–34.2 dB second-harmonic rejection, and −28.1 dB to −25.7 dB inter-channel crosstalk across 4.5–6.5 GHz. For a 100-MHz 256-QAM signal with 7.2 dB peak-to-average power ratio (PAPR), the PA achieves 29.9dBm average output power, 30% average PAE, −38.2/−39.1 dBc adjacent channel leakage ratio (ACLR), and −28.2 dB (3.9%) rms error vector magnitude (EVM), without using digital predistortion (DPD). Effect of crosstalk on linearity of the dual-channel PA is also measured and it is shown that for a 256-QAM signal EVM can increase by 3–8 dB, depending on relative power levels of the two channels.

High-Power Generation for mm-Wave 5G Power Amplifiers in Deep Submicrometer Planar and FinFET Bulk CMOS

A review is presented of the key techniques for high-power, high-efficiency millimeter-Wave (mm-Wave) 5G power amplifier (PA) design in deep submicrometer planar and FinFET bulk CMOS processes. The work utilizes a distributed unit cell-based layout technique for neutralized differential pairs and stacking transistors in bulk CMOS. This article also proposes a prediction of saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) and its corresponding maximized power-added efficiency (PAE) at 39 GHz for three candidate power combined architectures of three-stage PAs with two supporting prototype PAs fabricated in 16-nm FinFET and 28-nm planar bulk CMOS processes. The single-stage two-stack 16-nm FinFET PA generates a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 18.3 dBm from a 1.8-V supply at 39 GHz with a drain efficiency (DE) of 35.5%. The three-stage 28-nm PA incorporates a two-stack output stage with a balanced and compact 4-to-1 series-parallel combiner and achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 26 dBm using a 2.2-V supply, PAE of 26.6%, and high average power measurements with single-carrier and 5G new radio orthogonal frequency-division multiplexing modulations with competitive efficiencies. Long-term reliability measurements are performed using aging acceleration techniques to demonstrate the robustness of both prototypes. The competitive power and efficiency results, supported with reliability measurements, show that bulk CMOS can achieve performance comparable to SOI CMOS for generating high power at mm-Wave frequencies.

Balanced-to-Doherty Mode-Reconfigurable Power Amplifier With High Efficiency and Linearity Against Load Mismatch

A balanced-to-Doherty (B2D) mode-reconfigurable power amplifier (PA) is presented in this article, which is endowed with a unique capability of maintaining high linearity and high efficiency against load mismatch. The Doherty operation of this PA is based on a new Doherty PA (DPA) architecture configured from an ideal balanced amplifier, named quasi-balanced DPA (QB-DPA). This article, for the first time, analytically proves that the QB-DPA is functionally equivalent to a standard DPA. Most importantly, this new discovery enables PA reconfiguration between the Doherty and balanced modes. With the tunability implemented using a silicon-on-insulator (SOI)-based single-poledouble-throw (SPDT) switch, a reconfigurable B2D PA prototype using GaN technology is demonstrated at 3.5 GHz, exhibiting the state-of-the-art linear DPA performance in the nominal 50-Ω load condition. Specifically, the Doherty mode achieves a continuous-wave measurement efficiency of 70% and 54.5% at the maximum output power of 41.9 dBm and 6-dB power backoff, respectively. In the modulated long-term evolution (LTE) evaluation, the DPA exhibits -37-dB adjacent channel power leakage (ACPR) and 2.36% error vector magnitude (EVM) at the maximum rated power of 34.5 dBm while achieving a 42.4% efficiency. It is experimentally demonstrated that the Doherty (QB-DPA) mode is well resistant to load mismatch with high efficiency across a majority portion of the 2:1 voltage standing wave ratio (VSWR) circle, while the combination of Doherty and balanced modes can ensure a constantly linear performance of the B2D PA (e.g., 2.2%-5% of EVM) under the entire mismatch condition.

Under-FET Thermal Sensor Enabling Smart Full-Chip Run-Time Thermal Management

This article reports design, fabrication and analysis of a novel under-transistor (under-FET) in-hole thermal sensor diode structure. Being able to accurately monitor self-heating of individual transistor in-operando, the under-FET temperature sensor enables smart full-chip run-time thermal management with spatial resolution down to single transistor level. The in-hole thermal sensors were fabricated in a CMOS process and validated in measurements. The new chip level thermal management technique was demonstrated using a prototype power amplifier (PA) IC designed in a foundry 40nm CMOS. It opens a door for self-learning based full-chip real-time intelligent thermal management for future ICs.

Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

In this paper, a novel outphasing power amplifier (PA) based on class-E amplifiers with shunt capacitances and shunt filters is proposed. The new design provides high drain efficiency for both peak and back-off power levels. A mathematical model for the class-E power amplifier with shunt capacitance and shunt filter is presented. The proposed model enables derivation of load circuit parameters that provide optimum drain efficiency for the peak and back-off power levels using closed form mathematical expressions. Based on this model, an outphasing power amplifier is designed and subsequently implemented using microstrip transmission lines and a GaN HEMT devices. The fabricated power amplifier prototype is optimized for 2.14 GHz and provides drain efficiency of over 60% for back-off power levels up to 8.5 dB. The amplifier demonstrates a 44.3% drain efficiency for 64QAM OFDM modulated signal with 20 MHz bandwidth. Adjacent channel leakage ratio (ACLR) of −39.5 dB and error vector magnitude (EVM) of 0.9 % were achieved after the application of a memory polynomial linearization algorithm.

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier

This article presents a multi-subharmonic switching (SHS) digital power amplifier (PA) architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output power. The proposed phase-interleaved architecture provides the inherent cancellation of the subharmonic components in the PBO region, alleviating the burden of the matching network. The proposed multi-SHS scheme can be further combined with a class-G operation to create a greater number of efficiency peaks in the PBO region. A transformer-based, three-way power combiner and a triple-stacking class-D driver are utilized to obtain watt-level output power. The proof-of-concept PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS and achieved 30-dBm peak power at 1.9 GHz, with 45.9%/41.3%/35.3%/32.2%/24.2% drain efficiency located at 0-, -3.5-, -7.0-, -9.5-, and -12-dB PBO, respectively. The average efficiency was 31.4% in real-time operation with a 7.2-dB peak-to-average power ratio (PAPR) modulated signal.

A Super-Resolution Mixed-Signal Doherty Power Amplifier for Simultaneous Linearity and Efficiency Enhancement

This article presents a mixed-signal Doherty power amplifier (MSDPA) architecture for simultaneous linearity and efficiency enhancement. The MSDPA comprises one analog power amplifier (PA) as the main PA and one binary-weighted digital PA as the auxiliary PA. The MSDPA input is a generic envelope-varying complex-modulated signal. Based on the realtime amplitude-modulated (AM) envelope, auxiliary digital PA weightings are dynamically turned-on to perform optimum Doherty load modulation for superior linearity and back-off efficiency. Moreover, quantization noise is largely suppressed by the mixed-signal Doherty operation and nonuniform quantization (NUQ), while spectral images are substantially reduced by the quasi-first-order hold (quasi-FOH) operation, which together achieves super-resolution over conventional digital PAs; this makes the MSDPA conducive to millimeter-wave (mm-Wave) or compound PA designs by obviating the need for a large effective number of bits (ENOB) on AM digital controls. As a proof of concept, a 3-bit MSDPA is implemented at 27 GHz in a 45-nm silicon-on-insulator (SOI) CMOS process. The prototype PA achieves 40.1% peak power-added efficiency (PAE), 23.3-dBm saturated output power (Psat), and 39.4% PAE for 22.4-dBm P1dB at 27 GHz in continuous-wave (CW) measurements. The PAE at 6-dB power back-off (PBO) is 33.1%, which corresponds to a 1.68× improvement over a normalized Class-B PA. With only three control bits, the MSDPA PA supports a 12-Gb/s 64-QAM signal at -24.5-dB rms error vector magnitude (EVM) and average Pout/PAE of +15.6 dBm/27.8% without digital predistortion (DPD).

Generalized Class-E Power Amplifier With Shunt Capacitance and Shunt Filter

This paper presents a generalized analysis of the Class-E power amplifier (PA) with a shunt capacitance and a shunt filter, leading to a revelation of a unique design flexibility that can be exploited either to extend the maximum operating frequency of the PA or to allow the use of larger active devices with higher power handling capability. The proposed PA fulfills zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) conditions, resulting in a theoretical dc-to-RF efficiency of 100%. Explicit design equations for the load-network parameters are derived, and the analytical results are confirmed by harmonic-balance simulations. Two PA prototypes were constructed with one designed at low frequency and the other at high frequency. The first PA, which employs a MOSFET and a lumped-element load-network, delivered a peak drain efficiency $(\!D\!E)$ of 93.3% and a peak output power of 37 dBm at 1 MHz. The second PA, which employs a GaN HEMT and a transmission-line (TL) load-network to provide the drain of the transistor with the required load impedances at the fundamental frequency as well as even and odd harmonic frequencies, delivered a peak $D\!E$ of 90.2% and a peak output power of 39.8 dBm at 1.37 GHz.

Transformer-Based Predistortion Linearizer for High Linearity and High Modulation Efficiency in mm-Wave 5G CMOS Power Amplifiers

This paper presents a new predistortion linearization technique for high linearity and high modulation efficiency in millimeter-wave (mm-wave) CMOS power amplifiers (PA) for fifth-generation (5G) mobile communications. Our proposed linearizer adopts a transformer-based (i.e., inductive) self-compensated predistortion network at the input of the PA whose amplitude-modulation to phase-modulation (AM–PM) response is opposite compared with the AM–PM response of a CMOS PA, resulting in an AM–PM cancellation effect. This proposed inductive linearization method mitigates the large gain reduction problem in traditional capacitor-based linearization approaches while consuming no extra dc power or without introducing additional control circuitry. As a result, a significant improvement in power-efficiency and linearity is achieved with high-order complex modulation signals. To validate the proposed linearization method, a PA prototype in 65-nm CMOS technology was fabricated and tested, and it exhibited $\vert $ AM–PM $\vert $ distortion at $P_{\mathrm {o,1\, dB}}$ over 4 GHz of bandwidth (27–31 GHz). At 28 GHz, the measured saturated $P_{\mathrm {o}}$ and peak power-added-efficiency (PAE) was 15.6 dBm and 41%, respectively, while achieving a 6-dB $P_{\mathrm {o}}$ back-off PAE of 25%. To assess PA’s large-signal performance for 5G communications, the prototype was measured with the 64-quadratic-amplitude modulation (QAM) signal at 2-Gb/s data rates at 28 and 30 GHz, and the PA achieves modulated-PAE of 18.2%/17.6% and average- $P_{\mathrm {o}}$ of 9.8 dBm/10 dBm, respectively, while maintaining $2\times $ improvement in comparison with the recently reported 28-GHz linear CMOS PAs. Also, the PA occupies a compact active-area of 0.24 mm2.

Design Method of Self-Driving RF-DC Rectifier Based on Waveform-Guided Solutions to Passive Matching Network

The design of a self-driving RF-DC rectifier needs to synchronize the gate driving and RF power input. A waveform-based design method is proposed in this paper to get this synchronization through a direct network-parameter calculation of the coupling and matching circuit, other than introducing an adjustable phase shifter on its dual power amplifier prototype. In order to get a practical design at microwave band, nonlinear feedback capacitances, package parasitics, and device's I-V curves are considered in the large-signal RF-DC rectifier circuit analysis. The external passive matching network characterized by its Z -parameters can be determined in order to realize a specific high-efficiency operation mode, which is quantified by waveform distance. An RF-DC class-E rectifier example at 2.8 GHz is given to demonstrate this design method based on a modified GaN device model including negative drain voltages. Rectification efficiency of 70.8% is measured for a 10 W input power at 2.8 GHz.

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, -3.5, -9.5, and, -13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at -13-dB PBO.

Outside Nominal Operation Analysis and Design Considerations of Inverse-Class-E Power Amplifier

In this paper, design and analysis using analytical expressions for the inverse class-E power amplifier (PA) operating at the outside nominal operation, i.e., class- $\text{E}_{\mathrm{n}}$ PA, is presented. This operation is defined as nonzero current switch (n-ZCS) and nonzero-derivative-current switch (n-ZDCS) conditions. The generalized design equations as a function of design specifications, load resistance, and a given dc-supply voltage are derived. Two degrees of the design freedom achieved thanks to n-ZCS and n-ZDCS that are utilized for the simultaneous satisfaction of design specifications, such as peak-switch-voltage and peak-switch-current along with a given load resistance. The output power capability is affected by n-ZCS and n-ZDCS conditions, which can be obtained in the desired value using the controlled adjustment of introduced deviation parameters. In order to prove the validity of the proposed design methodology, an inverse class-E PA operating in 2 GHz with output power of 23 dBm is implemented in 0.25- $\mu \text{m}$ AlGaAs–InGaAs pHEMT technology. There is a close agreement between the theoretical and simulation results and the measurements of the fabricated prototype PA, which proved the validity of the obtained design expressions.

A design methodology of envelope tracking power amplifier based on harmonic impedance tuning

AbstractA design methodology of utilizing the harmonic impedance tuning for the envelope tracking (ET) power amplifier (PA) is proposed in this letter. Owing to the assistance of harmonic tuning, the PA efficiency can be enhanced obviously. Experimental results show that PA prototype exhibits higher than 60% efficiency in the 7‐dB backoff power region and 36% average efficiency including envelope amplifier (EA) when driven by a 7‐dB PAPR long‐term evolution (LTE) signal.

Novel Design Space of Load Modulated Continuous Class-B/J Power Amplifier

A novel design space of load modulated (LM) continuous Class-B/J power amplifiers (PAs) is proposed, and a detailed mathematical analysis is presented. The combination of LM technique and continuous mode is introduced to enhance the wideband performance of LM PAs. An inversely proportional relationship between $Z_{L}$ and $C_{\mathrm {out}}$ is derived, which indicates that the nonlinear $C_{\mathrm {out}}$ can affect the optimal load impedances at output power backoff (OPBO) and the design parameter $\beta $ should be appropriately adjusted. The measured results of a PA prototype show that the PAE is 39%–45% under LM when OPBO = 5 dB across 1.6–2.4 GHz. Compared with the same PA with fixed $V_{\mathrm {var}}$ , the proposed PA with optimum $V_{\mathrm {var}}$ at 2 GHz achieves a PAE improvement with 11% when OPBO = 5 dB.

A highly efficient concurrent dual-band GaN class-AB power amplifier at 1.84 GHz and 3.5 GHz

This article presents the design, simulation, implementation, and experimental results of a highly efficient, concurrent dual-band, gallium nitride (GaN), class-AB power amplifier (PA) at two frequencies: 1.84 and 3.5 GHz. It proposes a novel dual-band bandpass filter (DBBPF) with quad-section stepped-impedance resonators (SIRs) capable of rejecting the annoying frequencies of the second and third harmonics in the dual-band. The proposed DBBPF was applied in the design of a dual-band PA using a packaged 10 W GaN transistor. The PA prototype maintained a peak power-added efficiency (PAE) of 75.3% at the 1.84 GHz frequency and 64.5% at the 3.5 GHz frequency. For a continuous wave output power of 40.9 dBm, the measured gain was 13 dB in the two frequency bands. Linearized modulated measurements, concurrently using 10 MHz quadrature amplitude modulation (16 QAM) signals and worldwide interoperability for microwave access (WiMAX) signals, showed an average PAE of 48.5% and 39.8% and an adjacent channel leakage ratio of −46 and −45 dBc with an average output power of 37.8 and 36.8 dBm at the two frequency bands, respectively. This PA is used for wireless systems. It is especially useful in standard simultaneous global system for mobile (GSM) and WiMAX wireless systems.

Waveform Engineering at Gate Node of Class-J Power Amplifiers

In this paper, the class-J mode of operation is investigated when sinusoidal, half-sinusoidal (HS), triangle, pulse, and reduced conduction angle voltage waveforms are shaped at the gate node of the transistor. Output power, maximum power-added efficiency (PAE), large signal gain (LSG), and load–pull contours are presented and compared for each input signal. It is shown that PAE of a class-J power amplifier (PA) is improved when an HS voltage is realized at the gate node of the transistor. This enhancement can also be observed for a pulse input with 20% duty cycle, however, at the expense of reduced output power and LSG. A proof-of-concept, two-stage class-J PA is designed and fabricated in a 0.25- $\mu \text{m}$ AlGaAs-InGaAs pHEMT technology. The prototype PA is based on an HS gate voltage for the second-stage transistor, which operates in class-J mode. The driver stage also works in class-J mode to provide an HS voltage at its drain node, and the interstage matching network is designed to convey this waveform to gate of the second-stage transistor. Chip dimensions are $1.99\times1.24$ mm2, and 26.6–27.2-dBm output power with ≥50% PAE is achieved over the 0.92–1.4-GHz bandwidth.

A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation

This paper presents a mixed-signal power amplifier (PA) with real-time hybrid Class-G and dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency enhancement into the deep power back-off (PBO) region. Moreover, we dynamically manipulate the PA load impedance trajectory that travels from the optimum output power ( $P_{\mathrm {out}}$ ) load impedance to the optimum efficiency load impedance during PBO, which creates PA PBO efficiency peaking. The introduced digitally intensive mixed-signal PA architecture enables precise and optimum real-time hybrid PA operation and ensures both PA output amplitude and phase accuracy. DLTM operation also extends the PA RF carrier bandwidth. A prototype PA is fully integrated in a standard 65-nm bulk CMOS process. Its load modulation network is realized by an on-chip compact transformer balun and two on-chip switch-controlled capacitors. The PA achieves +24.6-dBm (+24.4-dBm) peak $P_{\mathrm {out}}$ and 45.6% (45.8%) maximum drain efficiency (DE) at 2.4 GHz (2.8 GHz). DLTM operation extends the PA $P_{\mathrm {out}}~{\mathrm{ and}}~1$ -dB bandwidth from 41.7% to 53.8%. By combining the real-time hybrid Class-G and DLTM operation with mixed-signal linearization, the PA delivers +17.6/+17.3-dBm (+17.3/+17-dBm) 10M-Sym/s 64QAM/256QAM at 2.4 GHz (2.8 GHz) with 27.5/26.7% (26.2/24.1%) DE, −29.2/−30.4-dB (−31.3/−31.5 dB) rms error vector magnitude (EVM), and −25.3/−25.1-dBc (−26.4/−26.1-dBc) adjacent channel leakage ratio (ACLR). The total chip area is 1.9 mm2.