A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation

Abstract

This paper presents a mixed-signal power amplifier (PA) with real-time hybrid Class-G and dynamic load trajectory manipulation (DLTM) operation that achieves PA efficiency enhancement into the deep power back-off (PBO) region. Moreover, we dynamically manipulate the PA load impedance trajectory that travels from the optimum output power ( $P_{\mathrm {out}}$ ) load impedance to the optimum efficiency load impedance during PBO, which creates PA PBO efficiency peaking. The introduced digitally intensive mixed-signal PA architecture enables precise and optimum real-time hybrid PA operation and ensures both PA output amplitude and phase accuracy. DLTM operation also extends the PA RF carrier bandwidth. A prototype PA is fully integrated in a standard 65-nm bulk CMOS process. Its load modulation network is realized by an on-chip compact transformer balun and two on-chip switch-controlled capacitors. The PA achieves +24.6-dBm (+24.4-dBm) peak $P_{\mathrm {out}}$ and 45.6% (45.8%) maximum drain efficiency (DE) at 2.4 GHz (2.8 GHz). DLTM operation extends the PA $P_{\mathrm {out}}~{\mathrm{ and}}~1$ -dB bandwidth from 41.7% to 53.8%. By combining the real-time hybrid Class-G and DLTM operation with mixed-signal linearization, the PA delivers +17.6/+17.3-dBm (+17.3/+17-dBm) 10M-Sym/s 64QAM/256QAM at 2.4 GHz (2.8 GHz) with 27.5/26.7% (26.2/24.1%) DE, −29.2/−30.4-dB (−31.3/−31.5 dB) rms error vector magnitude (EVM), and −25.3/−25.1-dBc (−26.4/−26.1-dBc) adjacent channel leakage ratio (ACLR). The total chip area is 1.9 mm2.