Post-silicon Validation Research Articles

Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers

Post-silicon validation is a vital step in System-on-Chip (SoC) design cycle. A major challenge in post-silicon validation is the limited observability of internal signal states using trace buffers. Hardware assertions are promising to improve observability during post-silicon debug. Unfortunately, we cannot synthesize thousands (or millions) of pre-silicon assertions as hardware checkers (coverage monitors) due to hardware overhead constraints. Therefore, we need to select the most profitable assertions based on design constraints. However, the design constraints can also change dynamically during the device lifetime due to changes in use-case scenarios as well as input variations. Therefore, assertion selection needs to dynamically adapt based on changing circumstances. In this article, we propose an assertion-based post-silicon validation framework to address the above challenges. Specifically, this article makes two important contributions. We propose a clustering-based assertion selection technique that can select the most profitable pre-silicon assertions to maximize the fault coverage. We also present a cost-aware dynamic refinement technique that can select beneficial hardware checkers during runtime based on changing design constraints. Experimental evaluation demonstrates that our proposed pre-silicon assertion selection can outperform state-of-the-art assertion ranking methods (Goldmine and HARM). The results also highlight that our proposed post-silicon dynamic refinement can accurately predict area (less than 5% error) and power consumption (less than 3% error) of hardware checkers at runtime. This accurate prediction enables the identification of the most profitable hardware checkers based on design constraints.

Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation

Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation

Logic Bug Detection and Localization Using Symbolic Quick Error Detection

We present Symbolic Quick Error Detection (Symbolic QED), a structured approach for logic bug detection and localization which can be used both during pre-silicon design verification as well as post-silicon validation and debug. This new methodology leverages prior work on Quick Error Detection (QED) which has been demonstrated to drastically reduce the latency, in terms of the number of clock cycles, of error detection following the activation of a logic (or electrical) bug. QED works through software transformations, including redundant execution and control flow checking, of the applied tests. Symbolic QED combines these error-detecting QED transformations with bounded model checking-based formal analysis to generate minimal-length bug activation traces that detect and localize any logic bugs in the design. We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using “difficult” logic bug scenarios observed in various state-of-the-art commercial multicore SoCs. Our results show that Symbolic QED: (i) is fully automatic, unlike manual techniques in use today that can be extremely time-consuming and expensive; (ii) requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; and (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques. Significantly, this new approach does not require any additional hardware.

SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs

SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs

An exquisitely sensitive variant-conscious post-silicon Hardware Trojan detection

Hardware Trojans, malicious modifications or additions to circuit elements, are often introduced during outsourced stages of IC manufacturing. Their presence in hardware security platforms became a concern after incidents like the Syrian RADAR failure and the Kill-switch incident. Existing Trojan detection techniques mostly focus on netlist-level identification and overlook process variation challenges in post-silicon ICs. In this work, we introduce a novel golden free and highly sensitive detection method that addresses process variations and various sources of noise. Our approach achieves enhanced detection sensitivity by (i) utilizing an efficient circuit partitioning method that takes into account post-silicon noises, ensuring post-silicon validation through pre-silicon analysis, (ii) implementing a technique to mitigate the impact of systematic and random variations within and between dies, (iii) developing a variation-aware test pattern generation approach that utilizes a bit-flipping technique, leading to low transition net switching and increasing the likelihood of activating Trojans. We evaluate the sensitivity of our detection approach using a custom tool called relative power difference (RPD). To validate our method, we conduct experiments on the ISCAS’89 benchmark and the AES-128 circuit, testing against various Trojans reported in the literature. Our results demonstrate outstanding detection sensitivity for inserted Trojans across different levels of noise.

Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems

In digital audio systems, filters and equalizers are essential modules for audio improvement at the input and output stages. Due to their computational complexity, most audio tasks are processed with digital signal processors. Due to the fact that latency in audio systems is a critical specification and audio trends require higher sample rates, noise canceling, and bigger data sizes, having an independent high-resolution equalizer would reduce the computational power needed for audio systems. This research had the goal of designing and implementing a hardware architecture for a configurable filter bank based on finite impulse response (FIR) filters and a noise-cancellation stage with an inter-integrated circuit (I2C) communication interface, which allows the filter configuration. The system was implemented as a standalone integrated circuit (IC) for which its inputs were the inter-IC sound (I2S) bus control signals. The digital audio system was optimized to perform one-cycle convolutional operations by implementing a vector–vector arithmetic logic unit. Furthermore, this applied research provides the register transfer level description and the functional verification of the digital design, the system-on-chip (SoC) implementation in TSMC 180 nm technology, and the post-silicon validation with a printed circuit board for testing the output digital signals of the system.

An Efficient Stress Pattern Based on VMRQ-PRBS for DDR Training

With increasing of clock rate and routing density, the problem of signal integrity in high-speed parallel links is becoming increasingly serious. Hence, the design of an effective input/output (IO) stress pattern is necessary in post-silicon testing and validation, which can identify circuit functional bugs quickly and provide adequate test coverage. In this article, an effective stress pattern based on the variable mark ratio quasi-pseudorandom bit sequence is proposed to train the center point of the received signal's eye diagram to obtain the best sampling timing and the reference voltage of double data rate memory. The stress pattern is divided into two parts, i.e., the stress pattern of the victim line that can excite the worst intersymbol interference (ISI) and the stress pattern of the aggressor line that can excite the worst cross talk. To validate the efficiency of the proposed stress pattern, it is compared to the victim–aggressor stress pattern based on pseudorandom binary sequence (PRBS). The measurement comparison shows that the pressure degree of the proposed stress pattern becomes more serious than that of the victim–aggressor stress pattern with increasing data rate.

A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive Validation

This article presents a wideband series-Doherty power amplifier (SDPA) for millimeter-wave (mm-wave) fifth-generation (5G) applications. It features a compact two-step impedance inverting-based series-Doherty power combiner that provides broadband close-to-perfect power back-off (PBO) efficiency enhancement. The amplitude-to-amplitude (AM–AM)/amplitude-to-phase (AM–PM) performance of the load-modulated Doherty power amplifier for broadband operation is analyzed. We also devise a post-silicon inter-stage passive validation (PSIV) approach to evaluate the mm-wave chip prototype utilizing the embedded voltage root mean square detectors. The proposed SDPA is realized in a 40-nm bulk CMOS, and it delivers 20.4 dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {SAT}}$ </tex-math></inline-formula> with 39.1%/34% PAE at 0-/6-dB PBO. Over a 23.5–30 GHz band, its PAE is >24% at 6-dB PBO. At 27 GHz, applying a “2 GHz 16-quadratic-amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM)” signal, the proposed SDPA generates 10.2 dBm average power with 18.9% average PAE. The average error vector magnitude is better than −24.5 dB without digital predistortion for a “400-MHz 64-QAM OFDM” signal while generating an average output power of 8.8 dBm with 15% PAE. The AM–AM/AM–PM of the realized SDPA is investigated by employing a “50-MHz 64-QAM OFDM” signal, validating our analysis and showing that the linearity limitation of DPAs is systematic and predictable. Utilizing the proposed PSIV approach, the frequency response of the input/inter-stage passive circuits is measured, indicating an excellent agreement with 3-D electromagnetic (EM) simulation results.

Fast Jitter Tolerance Testing for High-Speed Serial Links in Post-Silicon Validation

Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter circuitry in real system environments. One of the most common ways to evaluate the performance of an HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3.

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error-detection and, thus, it can speed-up the access-time of arrays that use in-line error-correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper introduces a two-dimensional error-correction scheme based on RTD and, also, presents a proactive error-correction method that combines RTD with demand-scrubbing. The work describes how to build RTD into a memory array with flip-flops to track in real-time the column-parity. A comparison of the proposed two-dimensional ECC scheme, as compared to single-error-correction-double-error-detection, shows that the RTD design has comparable error-detection-and-correction strength and, depending on the array dimensions and configuration, RTD reduces access time by 4% to 26% at an area and power overhead (negative is a reduction) between -7% to 33% and -42% to 86% respectively.

A Survey on Assertion-based Hardware Verification

Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this article, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements.

Low-Noise, High-Linearity Sine-Wave Generation Using Noise-Shaping Phase-Switching Technique

To develop a lower cost on-chip characterization solution for postsilicon validation, this article proposed a &#x201C;noise-shaping phase-switching&#x201D; technique on a sigma&#x2013;delta modulated digital-to-analog converter (DAC) to realize a low-noise, high-linearity sinusoidal-wave generator. The proposed technique combines the fifth-order cascade of resonators with distributed feedback (CRFB) type delta&#x2013;sigma modulation (DSM) and the two-way time-interleaving phase-switching harmonic distortion (HD) cancellation technique without additional cost. The theoretical analysis is verified with MATLAB and further implemented using a low-cost arbitrary waveform generator (AWG) as the output DAC. Compared with a nonideal 12-b DAC, the proposed technique achieved at least 2-dB enhancement in spurious-free dynamic range (SFDR) (measurement) while maintaining an improvement of at least 18 dB in the medium dynamic range (DR) (simulation) over the entire signal bandwidth.

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty

Due to limited on-chip caching, data-driven applications with large memory footprint encounter frequent cache misses. Such applications suffer from recurring miss penalty when they re-reference recently evicted cache blocks. To meet the worst-case performance requirements, Network-on-Chip (NoC) routers are provisioned with input port buffers. However, recent studies reveal that these buffers remain underutilised except during network congestion. Trace buffers are Design-for-Debug (DfD) hardware employed in NoC routers for post-silicon debug and validation. Nevertheless, they become non-functional once a design goes into production and remain in the routers left unused. In this article, we exploit the underutilised NoC router buffers and the unused trace buffers to store recently evicted cache blocks. While these blocks are stored in the buffers, future re-reference to these blocks can be replied from the NoC router. Such an opportunistic caching of evicted blocks in NoC routers significantly reduce the miss penalty. Experimental analysis shows that the proposed architectures can achieve up to 21 percent (16 percent on average) reduction in miss penalty and 19 percent (14 percent on average) improvement in overall system performance. While we have a negligible area and leakage power overhead of 2.58 and 3.94 percent, respectively, dynamic power reduces by 6.12 percent due to the improvement in performance.

Runtime Malware Detection Using Embedded Trace Buffers

Anti-virus software (AVS) tools are used to detect malware in a system. However, AVS are vulnerable to attacks. A malicious entity can exploit these vulnerabilities to subvert the AVS. Recently, hardware components such as hardware performance counters have been used for malware detection. In this article, we propose preempts malware by examining embedded processor traces (PREEMPT), a zero overhead, high-accuracy, low-latency technique to detect malware by repurposing embedded trace buffer (ETB), a debug hardware component available in most modern processors. The ETB is used for postsilicon validation and debug and allows us to control and monitor the internal activities of a chip, beyond what is provided by the input/output pins. PREEMPT combines these hardware-level observations with machine learning-based classifiers to preempt malware before it causes damage. The benefits of reusing ETB for malware detection include the increased robustness against attacks and no performance penalties. PREEMPT can detect malware on an OpenSPARC T1 core running Linux operating system with a F1-score of 96.6%.

An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment

Post-silicon validation is a major challenge due to finite controllability and observability of actual silicon and makes debug a complex task. The trace signals routed from CPUs and other sources are translated by sampling unit to time-stamped trace messages and stored in trace buffer. Time stamp generated is not the exact time at which event has occurred. Hence, trace data read from trace buffer in post-silicon environment is not accurate from debug perspective. This is corrected by finding the variable delay along with various paths observed between two viewpoints, one being the source at which the event occurs and the other being the destination where the event gets recorded. One method to achieve time accurate debug data is by correlating the time at which data transaction event occurs at the signal with the time at which the trace data for that particular transaction event gets time-stamped. The major advantage is the successful reconstruction of pre-silicon environment for that particular post-silicon environment and enabling data to be viewed on the fly.

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.

Topological Ordering Signal Selection Technique for Internet of Things based on Combinational Gate for Visibility Enhancement

In modern System on Chip (SoC) design consist of intelligence of products, Internet of Things (IoT) based devices, mobile phones, laptops, servers etc. This shrinking market reduces the design automation validation process. Signal selection is the most effective and challenging technique in post-silicon validation and debug. The vital problem prevailing in this method is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize the state reconstruction. To identify the trace signals, signal restoration is the extensive metric that has been used so far. Topology-based restoration method is proposed here to minimize the error detectionlatency which helps to select the trace signals with minimum error or even errorless. This method aid to detect more number of errors within limited number of clock cyclesthan the restoration only selection techniques.

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection

Incorporating on-chip trace buffers (TBs) helps to overcome the limited observability by tracing selected signals during post-silicon validation. The effectiveness of TB-based techniques largely relies on selection of appropriate trace signals. For processor-based systems, the selection becomes relatively easier because important signals can be identified. However, for a general digital block in a complex system-on-chip, recognizing necessary trace signals becomes extremely challenging and requires a systematic approach. Previous research on trace signal selection has mainly focused on improving reconstruction of unknown signal values with the help of traced signals. Even though it serves as a good selection principle, an effective signal selection must consider other important factors such as error detection (ED) with the traced signals, which in turn assist in localization and root-cause discovery. Additionally, from practical point of view, the signal selection algorithm needs to cater to factors like routing congestion and minimizing routing wire length. The proposed methodology of signal selection attempts to combine these three crucial factors of signal selection: restoration of untraced signal states, ED with traced signals and routing considerations. The concurrent maximization of all these three parameters is difficult as they have conflicting preference of the candidate trace signals. Hence, the proposed signal selection approach presents a methodology of judiciously mixing the choices of these three objectives. Furthermore, the restored and traced signal states are analyzed for the purpose of error localization at the gate level for several design error models.

Метод валидации в кремнии библиотек стандартных цифровых элементов

Метод валидации в кремнии библиотек стандартных цифровых элементов

Predicting ${X}$ -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach

Digital circuits are often prone to suffer from uncertain timing, inadequate sensor feedback, limited controllability of past states or inability of initializing memory-banks, and erroneous behavior of analog-to-digital converters, which may produce an unknown ( ${X}$ ) logic value at various circuit nodes. Additionally, many design bugs that are identified during the post-silicon validation phase manifest themselves as ${X}$ -values. The presence of such ${X}$ -sources on certain primary or secondary inputs of a logic circuit may cause loss of fault-coverage of a test set, which, in turn, may impact its reliability and robustness. In this paper, we provide a mechanism for predicting the sensitivity of ${X}$ -sources in terms of loss of fault-coverage, on the basis of learning only a few structural features of the circuit that are easy to extract from the netlist. We show that the ${X}$ -sources can be graded satisfactorily according to their sensitivity using support vector regression, thereby obviating the need for costly explicit simulation. Experimental results on several benchmark circuits demonstrate the efficacy, speed, and accuracy of prediction.