Post-cursor Intersymbol Interference Research Articles

A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS

This article presents a four-level pulse-amplitude modulation (PAM-4) transceiver targeting very-short-reach and medium-reach (MR) electrical links. The receiver (RX) employs a sample-based four-tap feed-forward equalizer (FFE) for pre- and post-cursor inter-symbol interference (ISI) compensation. The two-stage 16-way interleaving provides sufficient operation time for FFE summation, which relaxes the bandwidth (BW) requirement and improves power efficiency. The non-uniform segmented three-tap FFE reduces the parasitic capacitance in the transmitter (TX). The one-unit interval (UI)-pulse generator in the 4:1 multiplexer uses a pre-charge phase to achieve a fast edge with single-stage logic. Fabricated in 28-nm CMOS technology, the transceiver achieves a bit error rate (BER) of < 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$e-11$ </tex-math></inline-formula> at 112-Gb/s transmission with a channel loss of 20.8 dB and an energy efficiency of 2.29 pJ/b.

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

A controller PHY for high-capacity DRAM is presented. To reduce precursor and postcursor intersymbol interference due to its dispersive channel characteristics and a heavy load of many DRAM chips and to attenuate reflection on a highly reflective command/address (C/A) channel, a damping-resistor-aided three-tap pulse-based feed-forward equalizer (PB-FFE) is introduced. An appropriate damping resistance can attenuate reflection, and the PB-FFE compensates for increased insertion loss due to the damping resistor. In addition, the current flows only before and after a signal transition in the PB-FFE, improving energy efficiency and maintaining the turn-ON resistance during the no-transition region. A controller PHY based on this equalizer was fabricated in a 55-nm CMOS process. The PB-FFE increases the timing margin of the C/A signal from 0.23 to 0.29 UI at 1067 Mb/s. At 2133 Mb/s, the read timing and voltage margins of the DQ signal are 0.53 UI and 211 mV after read training, and its write margin is 0.72 UI and 230 mV, respectively, after write training.

Pin‐efficient 9‐bit 8‐wire 4‐level synergetic‐equalisation coding scheme for 216 Gb/s PAM4 transceiver

A synergetic-equalisation coding scheme for pulse-amplitude modulation 4-level (PAM4) is proposed, based on which a 216 Gb/s 9-bit 8-wire 4-level (9B8W4L) transceiver is designed. According to the scheme, eight channels are grouped into four pairs based on the states for encoding. The two channels in pair transmit the same symbol in this unit interval (UI), and transmit different symbols in different pairs in the next UI. When decoding, the symbols in different channels are subtracted from and added with the others, following the grouping in the prior UI. From this, the first post-cursor inter-symbol interference is eliminated. Based on the proposed coding scheme, the PAM4 transceiver transmits 9-bit data by eight channels, giving a channel utilisation of 112.5%. The improvement of channel utilisation reduces the Nyquist frequency for the same data rate, which is of great significance for reducing channel loss and power consumption. The 216 Gb/s 9B8W4L transceiver with 1-tap feed-forward equaliser achieves a bit error rate <10−12 through −20 dB channel loss at the Nyquist frequency of 12 GHz.

A Body Channel Communication Technique Utilizing Decision Feedback Equalization

This article presents the body channel communication technique that first adopts decision feedback equalisation. For the first time, we characterised post-cursor intersymbol interference of a single-bit pulse response of a human body channel for decision feedback equalisation achieving the first body channel communication faster than 100 Mb/s. In the proposed technique, an 8-tap decision feedback equaliser is utilised at the receiver to compensate for intersymbol interference of the body channel. The experimental results show that the proposed prototype transceiver achieved the highest data rates of 150 Mb/s and 10 Mb/s along 20-cm and about 100-cm body channels, respectively. Compared to the previous best result measured for the same body-channel distance of about 100 cm, the data rate is improved by ten times, showing that the proposed technique can significantly increase the speed of body channel communication.

A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS

While four-level pulse amplitude modulation (PAM4) standards are emerging to increase bandwidth density, the majority of standards use simple binary non-return-to-zero (NRZ) signaling. This paper presents a dual-mode NRZ/PAM4 serial I/O SerDes which can support both modulations with minimum power and hardware overhead relative to a dedicated PAM4 link. A source-series-terminated transmitter achieves 1.2- $\text{V}_{\mathrm {{pp}}}$ output swing and employs lookup table control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The receiver implements an NRZ/PAM4 decision feedback equalizer that employs one finite impulse response and two infinite impulse response taps for first post-cursor and long-tail inter-symbol interference (ISI) cancellation, respectively. First post-cursor ISI cancellation is performed in these comparators to optimize the design’s timing, while the remaining ISI taps are subtracted in a preceding current integration summer for improved sensitivity. Fabricated in GP 65-nm CMOS, the transceiver occupies 0.074 mm2 area and achieves 16 Gb/s NRZ and 32 Gb/s PAM4 operation at 10.9 and 5.5 mW/Gb/s while operating over channels with 27.6 and 13.5 dB loss at Nyquist, respectively.

A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE

Implementation of highly integrated optical receivers in CMOS promises low cost, but combining high gain, low noise, high bandwidth, and low power in a CMOS transimpedance amplifier is a challenge. Fortunately, the sensitivity of an optical receiver is improved by limiting its front-end bandwidth far below the symbol rate and using equalization to eliminate the resulting intersymbol interference (ISI). Analysis reveals that when using a decision-feedback equalizer (DFE) to cancel all postcursor ISI, receiver sensitivity is optimized by taking a front-end bandwidth as low as 0.12 ${f}_{\mathrm{ bit}}$ , depending upon the frequency response and noise spectrum assumed for the front end. This paper presents a 20 Gb/s optical receiver with a front-end bandwidth of 3 GHz. The front end is designed to have an approximately first-order response, ensuring only postcursor ISI, which may be efficiently canceled with a first-order infinite-impulse response DFE (IIR-DFE). An IIR-DFE circuit is also proposed that obviates the need for an explicit full-rate multiplexor. Fabricated in 65 nm CMOS, the receiver achieves 0.705 pJ/b efficiency with the IIR-DFE consuming 150 fJ/b. Using a photodiode with 12 GHz analog bandwidth and responsivity of 0.5 A/W, the receiver has a sensitivity of −5.8 dBm optically modulated amplitude.

Feedback delay reduction of Tomlinson–Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic

The data rate of a Tomlinson–Harashima (TH) precoder is limited by the delay in the feedback path of its infinite impulse response (IIR) filter that cancels the channel's post-cursor intersymbol interference (ISI). One reason for long loop delays is the requirement to perform the ISI subtraction from the data signal in binary arithmetic in order to properly execute the modulo (MOD) operation, which stabilises the IIR filter and limits the transmitter amplitude. The restriction to binary arithmetic is unfortunate, because some filter subcomponents such as, e.g. adder trees are often implemented in a faster data format that has no slow carry propagation [e.g. the carry-save adder (CSA) format]. This paper proposes a novel architecture for TH precoders in which the MOD operation is taken out of the loop, so that the remaining IIR filtering is performed entirely in CSA arithmetic to reduce the feedback delay as no conversion to binary format is required within the loop. With the pipelining technique applied, the filter's feedback delay reduces to the propagation delay of a multiply-accumulate unit operated with CSA arithmetic. The proposed concept was verified in a 14 nm CMOS test chip with multi-level signalling (NRZ, 4-/8-/16-PAM).

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS

An ideal infinite impulse response (IIR) decision feedback equalizer (DFE) can have an effect on wireline received waveforms similar to a continuous-time equalizer, but without the associated amplification of noise and crosstalk. However, an IIR DFE's performance degrades significantly as the feedback loop delay increases. Fortunately, adding a single discrete-time tap can eliminate the degradation. The implementation of a half-rate DFE with two IIR taps and one discrete-time tap is presented here. The two IIR filters have different time constants to accommodate a variety of channel pulse responses having a long tail. The discrete-time tap cancels the first post-cursor inter-symbol interference (ISI) term and alleviates feedback loop timing issues. The DFE can receive data transmitted with a low swing of 150 mVpp-diff through 24 dB of channel loss at half the bitrate while consuming 4.1 mW at 10 Gb/s. Digital foreground calibration of clock phase shifters and offset cancellation is described. The receiver, including the DFE, clock buffers and clock phase adjustment, occupies an area of 8760 µm 2 in an ST 28 nm LP CMOS process.

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Tomlinson-Harashima (TH) precoding is a transmitter equalization technique in which the post-cursor intersymbol interference (ISI) is canceled by means of an infinite impulse response (IIR) filter with modulo (MOD)-based amplitude limitation. TH equalizers are suited for asymmetric links, such as DRAM interfaces, where the transmitter contains the equalization complexity and the receiver is kept simple. To increase the data rate, we propose the application of pipelining and half-rate operation to the ISI subtraction in the equalizer's feedback path. A TH equalizer with 8 taps, 6 bit resolution, and 2-PAM/4-PAM support has been implemented in 22-nm silicon-on-insulator (SOI) CMOS technology. In measurements, the feedback delay reduction techniques allow us to equalize 34-cm-long PCB traces having 12-dB loss with 7 × ISI reduction for 5.0-Gb/s 2-PAM signaling, and in 10.0-Gb/s 4-PAM mode completely closed eye diagrams are opened. The measured efficiency of the 145 μm× 115 μm transmitter is 1.2 pJ/bit in 4-PAM mode at 5.0 Gbaud with disabled equalization and increases linearly with 14 μW/Gbaud per 1% increase of the equalization tap weights.

Precursor inter-symbol interference removal by block transmission-based time-reversed equalization

Single-carrier transmission is considered in the general finite impulse response inter-symbol interference (ISI) channel. In an ISI channel with a matched filter, the folded spectrum of the received pulse can be factored into a minimum phase causal part and a maximum phase anticausal part corresponding to the postcursor and precursor ISI, respectively. In this paper, zero-forcing ISI cancellation is considered. In a direct implementation, the precursor equalization is carried out based on truncating and delaying the ideal anticausal precursor equalizer impulse response. In the proposed scheme, a block transmission is adopted, and the precursor equalization is carried out by a time reversal within each block and using a practical minimum phase filter. We show that the ISI can be removed perfectly using the proposed scheme. By means of a numerical example, it is shown that the proposed scheme achieves improved performance compared to the truncate- and delay-based equalizer in terms of transmission rate, delay, and implementation complexity.

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link

This paper introduces a novel signaling scheme for parallel high-speed interfaces. The new signaling, called coded differential (CD), maps two bits of information to four wires and, therefore, has the same pin-efficiency as differential signaling. The coding scheme is designed in such a way that the parallel interface preserves many of the attractive properties of a differential link such as low supply noise generation and immunity to common-mode noise. The CD receiver also incorporates differential detection with no need for a dc reference. In addition, the coding completely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, CD leads to substantial increase in timing margin compared with a differential link with 1-tap decision feedback equalizer (DFE). Unlike DFE, CD does not require channel tap estimation. The theory of CD signaling, the optimization of the encoder and the decoder, and the implementation details of a prototype system developed based on this scheme for graphics memory interfaces are described. The full-featured interface, implemented in a 40-nm CMOS process, transfers 8 × 16 Gb/s data over 16 wires and achieves an energy efficiency of 4.1 pJ/b. Eye diagram measurements on a scope indicate 30% improvement in timing margin compared with a 1-tap predictive DFE system.

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor intersymbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory. In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory. The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5 × energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation.

Spatial-temporal fractionally spaced decision-feedback equalisation for fading channels with dispersive interference

The authors study the spatial-temporal minimum mean square error decision-feedback equaliser (ST-DFE) to combat dispersive interference over fading channels. The proposed ST-DFE consists of an anticausal fractionally spaced feedforward filter (FFF) on each antenna branch to perform co-channel interference (CCI) and precursor intersymbol interference (ISI) cancellation, followed by a symbol-spaced feedback filter to remove postcursor ISI. An optimum ST-DFE with a double-sided symbol-spaced FFF demonstrates excellent CCI/ISI cancellation ability, but occupies wider time span and is too complicated to implement in practice. Several ST-DFE schemes using the anticausal symbol-spaced FFF were proposed, but the simulation reveals that such an approach is unable to eliminate dispersive CCI efficiently and even performs substantially worse than spatial-temporal linear equalisers, when the continuous transmitted pulse shape is considered. The performance might become worse owing to the error propagation. The proposed ST-DFE is capable of improving the performance significantly, and even outperforms the double-sided symbol-spaced ST-DFE. The algorithm for computing the fractionally spaced coefficients is presented and then applied to the fast error probability calculation using the Gauss quadrature rule which can approximate the probability of the density function of the residual ISI and CCI. Such an approach avoids the interference characteristic of the inaccurate Gaussian method.

Frequency-Domain Equalization with Iterative Block Noise-Prediction for Single-Carrier Systems

In this letter, we propose a novel frequency-domain equalizer (FDE) for single-carrier systems characterized by severe inter-symbol interference (ISI) channels; it consists of a linear FDE and an iterative block noise-predictor (IBNP). Unlike the FDE with time-domain noise predictor (FDE-NP), the proposed scheme allows the feedback equalizer being an uncausal filter, and performs the noise prediction in an iterative manner. For this reason, FDE-IBNP can remove both precursor and postcursor ISI, and alleviate the impact of error-propagation. Besides, our scheme has lower computational complexity than the present iterative block equalizers.

Iterative decision feedback equalisation with no feedback filter

An iterative modified decision feedback equaliser (I-MDFE) with no feedback filter over broadband channels is proposed. Generally, in the structure of an I-DFE, a soft residual postcursor intersymbol interference (ISI) is removed by a feedback filter (FBF). However, the ISI in the I-MDFE is precancelled prior to the equalisation, which results in no requirement of the FBF. It is demonstrated in the simulation evaluation that the I-MDFE can offer excellent performance under the broadband channel, with shorter filter taps than those of an iterative linear equaliser (I-LE) and the I-DFE.

Single Carrier Frequency Domain Equalization with Time Domain Noise Prediction for Wideband Wireless Communications

Recent research has shown that single carrier frequency domain equalization (SC-FDE) is an attractive technology for broadband wireless communications for its advantages such as lower peak-to-average power ratio and reduced sensitivity to carrier frequency offset, when compared to orthogonal frequency-division multiplexing (OFDM) systems. In this paper, we propose a novel structure, FDE-NP, which consists of a linear frequency domain equalizer (FDE) and a time domain noise predictor (NP). It is shown that the proposed scheme has lower complexity and achieves better performance and complexity trade-off than the conventional FDE designs. In particular, by using a simple block interleaver/deinterleaver pair to rearrange the order of the received signals prior to decoding, delayed reliable decisions can be fed back to predict and cancel their post-cursor inter-symbol interference (ISI) effects to the following signals. Simulation results show that the proposed FDE-NP scheme achieves 1.5-2 dB performance improvement over the conventional FD-LE and FD-DFE schemes. Furthermore, we extend the design of unbiased and biased time domain equalizers (TDEs) into the frequency domain and propose the unbiased FDE. It is shown that although the unbiased FDE has a larger MSE than the biased one, it reduces the required SNR by about 0.3 dB in some cases

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique

Among existing works of high-speed pipelined adaptive decision feedback equalizers (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or other look-ahead approaches. For example, Shanbhag and Partiz derived three pipeline ADFE structures (PIPEADFE1, 2, 3), where PIPEADFE2 yields very good performance in terms of convergence rate and hardware cost. Nevertheless, the PIPEADFE2 employs Approximation Methods in deriving the Preprocessing Unit (PP). In this paper, a new pipelining ADFE architecture is developed. We derive a new updating ADFE scheme based on the Principle of Orthogonality. By employing the postcursor processing filter (PCF) to cancel the most significant postcursor Intersymbol interference (ISI) terms, the proposed PCFADFE architecture can significantly improve the convergence rate of the ADFE. Compared with PIPEADFE2, it has better convergence rate while at similar hardware cost. Hence, it provides an alternative approach for the design of high-speed pipelining ADFE with arbitrary speedup factor.

Optimum Infinite-Length MMSE Multi-User Decision-Feedback Space-TimeProcessing in Broadband Cellular Radio

We present an investigation of space-time receiver architectures in multi-user wireless systems where optimal idealized (infinite-length) space-time filtering is applied to minimize the mean-square error (MSE). Feedforward, decision-feedback and cross-decision feedback filters are employed; hence, the system eliminates the post-cursor ISI (intersymbol interference) and CCI (co-channel interference). While this is a form of MIMO-DFE (Multi-Input Multi-Output Decision-Feedback Equalization), no joint transmitter-receiver optimization is performed since the transmit sources are assumed to be individual users. Our analysis leads to an entirely novel closed-form expression for the minimum achievable MSE for any single user in both fully- and partially-connected cross-decision feedback systems (XDF). This differs from previous results on MIMO-DFE obtained in a CDMA context which rely on the Gaussian assumption. Numerical results compare the performance of XDF systems with standard space-time DF and linear processing as well as the MIMO matched-filter bound in both a generic Rayleigh-fading system context and a broadband wireless context with fixed, highly directional subscriber antennas and correlated fading based on a 3D channel model parameterized according to measurements at 29.5 GHz. Results indicate that generally, an N-element array with fully-connected XDF processing provides the same performance as an N+1-element array with standard linear space-time processing.

A class of block-iterative equalizers for intersymbol interference channels: fixed channel results

A new and efficient class of nonlinear equalizers is developed for intersymbol interference (ISI) channels. These -"iterated-decision equalizers" use an optimized multipass algorithm to successively cancel ISI from a block of received data and generate symbol decisions whose reliability increases monotonically with each iteration. These equalizers have an effective complexity comparable to the decision-feedback equalizer (DFE), yet asymptotically achieve the performance of maximum-likelihood sequence detection (MLSD). We show that, because their structure allows cancellation of both precursor and postcursor ISI, iterated-decision equalizers outperform the minimum mean-square error DFE by 2.507 dB on severe ISI channels even with uncoded systems. Moreover, unlike the DFE, iterated-decision equalizers can be readily used in conjunction with error-control coding, making them attractive for a wealth of applications.