A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS

Abstract

An ideal infinite impulse response (IIR) decision feedback equalizer (DFE) can have an effect on wireline received waveforms similar to a continuous-time equalizer, but without the associated amplification of noise and crosstalk. However, an IIR DFE's performance degrades significantly as the feedback loop delay increases. Fortunately, adding a single discrete-time tap can eliminate the degradation. The implementation of a half-rate DFE with two IIR taps and one discrete-time tap is presented here. The two IIR filters have different time constants to accommodate a variety of channel pulse responses having a long tail. The discrete-time tap cancels the first post-cursor inter-symbol interference (ISI) term and alleviates feedback loop timing issues. The DFE can receive data transmitted with a low swing of 150 mVpp-diff through 24 dB of channel loss at half the bitrate while consuming 4.1 mW at 10 Gb/s. Digital foreground calibration of clock phase shifters and offset cancellation is described. The receiver, including the DFE, clock buffers and clock phase adjustment, occupies an area of 8760 µm 2 in an ST 28 nm LP CMOS process.