Polysilicon Electrodes Research Articles

Characterization of Thermal and Electrical Stability of MOCVD HfO2 ­ HfSiO4 Dielectric Layers with Polysilicon Electrodes for Advanced CMOS Technologies

The thermal and electrical stability of dielectric layers with polysilicon electrodes are investigated in view of their use as gate dielectrics in advanced complementary metal oxide semiconductor (CMOS) technologies. The layers were deposited on 1 nm silicon oxide layers using metallorganic chemical vapor deposition (MOCVD). In situ p-doped polysilicon electrodes were deposited using rapid thermal chemical vapor deposition and low pressure chemical vapor deposition, respectively. The influence of rapid thermal annealing and postdeposition annealing of the high-k layers was investigated using MOS capacitors. The lowest equivalent oxide thickness was around 19.3 Å with a leakage current reduction of approximately 1000 times as compared to MOSFETs fabricated using a standard direct gate etch approach were used to study the stability of the dielectric and device properties as functions of activation anneal and implant conditions. A major problem was found to be the stability of the threshold voltage After 50 consecutive dc sweeps from −1 to +2 V, the threshold voltage of n-MOS devices shifted 50-200 mV. Using pulsed measurement technique, a hysteresis on the order of 300-400 mV was found. Only a minor improvement was achieved by different annealing of the layers. In conclusion, it was found that these layers exhibit unacceptably high instability to provide a solution as a gate dielectric for advanced CMOS technologies. © 2004 The Electrochemical Society. All rights reserved.

HfSiO4 Dielectric Layers Deposited by ALD Using HfCl4 and NH 2 ( CH 2 ) 3Si ( OC 2 H 5 ) 3 Precursors

The physical and electrical properties of dielectric layers deposited by atomic layer deposition (ALD) are reported. The precursor chemistries used for deposition were for and for Two processes with precursor pulse ratios of -rich”) and -rich”) are investigated. Measurements with X-ray photoelectron spectroscopy and channeling Rutherford backscattering spectrometry show that these processes result in layers with ratios of 0.56 and 0.34-0.37, respectively. X-ray diffraction measurements showed formation of a cubic phase in -rich layers starting at 850°C. In -rich layers, no crystallization was detected up to 1100°C. Metal oxide semiconductor (MOS) capacitors with polysilicon electrodes were used for electrical characterization. The k-value of the -rich layers was found to be 4.8-5.4 and that of the -rich layers 12.5-15.1, both with an experimental error of 10%. The leakage currents of both types of layers were comparable to reference data and increased with polysilicon activation anneal. A high-resolution transmission electron microscopy study revealed phase segregation in thick -rich layers. In -rich layers, the phase segregation was less clear, but upon annealing, composition variations at the interfaces were detected. Given the experimental errors, no impact of phase segregation on the k-values of both types of layers could be detected. It is concluded that postdeposition annealing of layers for application as gate dielectrics applications in advanced complementary MOS technologies is essential to optimize stoichiometry and reduce leakage currents. © 2004 The Electrochemical Society. All rights reserved.

Effects of Electrical Leakage Currents on MEMS Reliability and Performance

Electrostatically driven MEMS devices commonly operate with electric fields as high at 10/sup 8/ V/m applied across the dielectric between electrodes. Even with the best mechanical design, the electrical design of these devices has a large impact both on performance (e.g., speed and stability) and on reliability (e.g., corrosion and dielectric or gas breakdown). In this paper, we discuss the reliability and performance implications of leakage currents in the bulk and on the surface of the dielectric insulating the drive (or sense) electrodes from one another. Anodic oxidation of poly-silicon electrodes can occur very rapidly in samples that are not hermetically packaged. The accelerating factors are presented along with an efficient early-warning scheme. The relationship between leakage currents and the accumulation of quasistatic charge in dielectrics are discussed, along with several techniques to mitigate charging and the associated drift in electrostatically actuated or sensed MEMS devices. Two key parameters are shown to be the electrode geometry and the conductivity of the dielectric. Electrical breakdown in submicron gaps is presented as a function of packaging gas and electrode spacing. We discuss the tradeoffs involved in choosing gap geometries and dielectric properties that balance performance and reliability.

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO 2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high- k gate dielectric transistors were investigated. The performance of O 3 vs. HF-last/NH 3 pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO 2 gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high- k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO 2 microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO 2/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high- k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.

An Improved CCD Register Driven from Overflow Drain through Barrier.

Conventional CCD registers for full frame or frame transfer scheme image sensors have disadvantages such as low light sensitivity due to light absorption in electrodes, high dark current generated at Si-Si02 interfaces, and small charge handling capability that results from the surface pinning mode of operation. To solve these problems, we proposed CCD register driven through a barrier in February 2000. The register cell was an inverted version of the photo-diode with a vertical overflow drain that is used as the driving electrode. In simulating the register's characteristics in back illumination mode, we found that all the above-disadvantages disappeared, but the characteristics were rather sensitive to the height, width, and location of SiO2 film required to isolate electrodes. Therefore, some difficulty remains in fabrication processes. This paper proposes a new version of DTB-CCD where a specific-feature SiO2 layer covers a part of the barrier surface. This layer not only helps to minimize the structure sensitiveness of performance but also makes it possible to employ the conventional overlapping poly-Silicon electrode process. A thin SiO2 layer between electrodes and optimized width and thickness of the Si02 layer on the barrier minimizes potential barrier height in channels and thus improve transfer efficiency. The simulated charge handling capability of the improved DTB-CCD was 3-4 times greater than that of a two-phase CCD register driven by surface pinning mode.

Fast interface characterization of tunnel oxide MOS structures

As new gate materials become increasingly interesting in conjunction with tunnel oxides, a fast and reliable interface characterization technique becomes indispensable. Fast turnaround times require a method which can be applied to simple test structures like planar capacitors. For the first time, we demonstrate an automatic extraction of physical oxide thickness and flatband potential from capacitance-voltage measurements which includes quantum confinement effects and Fermi-Dirac statistics. Automatic extraction is necessary for uniformity analysis across a whole wafer. New gate materials are typically binary or ternary alloys where the interface to the gate dielectric is very sensitive to deposition parameters. Such systems are likely to show higher nonuniformities than polysilicon electrodes. An example is presented where polysilicon gates exhibit a uniformity in flatband potential within a wafer of less than /spl plusmn/15 mV while a thickness variation of 0.1 nm has been observed.

N and P metal oxide semiconductor field effect transistor characteristics of hafnium-doped SiO2 gate dielectrics

This work presents the interfacial properties of hafnium-doped SiO2 films via N and P metal oxide semiconductor (MOS) materials, MOS-capacitor, and N and P metal oxide semiconductor field effect transistor (MOSFET) characterization. The results indicate that HfSixOy films (a) have excellent transistor characteristics; (b) remain amorphous through high-temperature processing; (c) are compatible with N+ and P+ polysilicon electrodes; (d) have lower gate leakage than SiO2 of the same equivalent oxide thickness (EOT); and (e) have a dielectric constant of ∼8. Therefore, the hafnium-doped SiO2 films are at-tractive as a dielectric material and offer a technologically relevant gate-stack node for insertion, prior to deployment of high-K dielectrics.

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process.

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

High aspect-ratio combined poly and single-crystal silicon (HARPSS) MEMS technology

This paper presents a single-wafer high aspect-ratio micromachining technology capable of simultaneously producing tens to hundreds of micrometers thick electrically isolated poly and single-crystal silicon microstructures. High aspect-ratio polysilicon structures are created by refilling hundreds of micrometers deep trenches with polysilicon deposited over a sacrificial oxide layer. Thick single-crystal silicon structures are released from the substrate through the front side of the wafer by means of a combined directional and isotropic silicon dry etch and are protected on the sides by refilled trenches. This process is capable of producing electrically isolated polysilicon and silicon electrodes as tall as the main body structure with various size capacitive air gaps ranging from submicrometer to tens of micrometers. Using bent-beam strain sensors, residual stress in 80-/spl mu/m-thick 4-/spl mu/m-wide trench-refilled vertical polysilicon beams fabricated in this technology has been measured to be virtually zero. 300-/spl mu/m-long 80-/spl mu/m-thick polysilicon clamped-clamped beam micromechanical resonators have shown quality factors as high as 85 000 in vacuum. The all-silicon feature of this technology improves long-term stability and temperature sensitivity, while fabrication of large-area vertical pickoff electrodes with submicrometer gap spacing will increase the sensitivity of micro-electromechanical devices by orders of magnitude.

Electrical Properties of Polysilicon Electrodes for Conductometric Measurement

The miniaturized polysilicon electrodes for conductometric sensors have been fabricated by standard CMOS process. The interface impedance of polysilicon and saline solution (0.9 % NaCl) are measured in the frequency range of 100 Hz–1 MHz. At this frequency range, the impedance can be described as K/((iω)β, where K is around 33 MΩ Hz0.93 and β is about 0.93 for the electrode area of 2 mm2. Compared to Pt black and Pt electrode, the impedance of polysilicon electrodes is quite large. This is supposedly due to the formation of silicon oxide layer at the surface of polysilicon electrodes in saline solution. The response of a pair of polysilicon electrodes to 0–75 mM KCl in saline solution at 20 KHz has good linearity. With the deposition of urease on the top of the pair of polysilicon electrodes, it is also possible to detect urea concentration with this conductometric setup.

Issues in the Flexible Integration of Sputter-Deposited PZT Thin Films with Polysilicon and Ti/Pt Electrode Layers for Use as Sensors and Actuators in Microelectromechanical Systems (MEMS)

ABSTRACTSputter-deposited piezoelectric lead zirconate titanate (PZT) thin films with Ti/Pt and polysilicon electrode layers are being investigated for use in Microelectromechanical Systems (MEMS). Existing research shows the nucleation of the perovskite phase of the PZT is linked to the lattice spacing of the underlying Pt electrode and/or seed layers, and is key in obtaining PZT layers with good piezoelectric/ferroelectric properties. Our research with piezoelectric PZT films on Ti/Pt electrode layers aims at employing these films to generate and receive acoustic waves in flexural plate wave devices (FPWs). Our experiments indicate the formation of a random polycrystalline perovskite phase is linked to the emergence of oriented <100> Pt grains within the dominant <111>-oriented crystal structure during rapid thermal annealing in an oxygen environment. Pt films annealed in nitrogen, in contrast, retained their <111> preferential orientation without the formation of Pt <100> grains. PZT films deposited on these electrodes and annealed in nitrogen were strongly oriented in the <111> direction, but exhibited lossy ferroelectric behavior and were prone to delamination. We are also investigating the feasibility of using doped polysilicon electrode layers with PZT thin films. The multiple layers used with the Pt electrode (Pt, Ti, and SiO2 adhesion layer) have significant interactions with one another, and replacing these layers with a single electrode layer should alleviate these complications. A low-temperature PZT deposition process (300°C) and short annealing cycles (30 sec.), coupled with a TiO2 barrier/seed layer should prevent interdiffusion and reactions between the polysilicon and PZT layers. Our experiments show that PZT films deposited and annealed on doped polysilicon layers develop a random polycrystalline perovskite phase, but are subject to tensile cracking. The use of polysilicon as an electrode layer should also facilitate the integration of piezoelectric PZT layers with polysilicon surface micromachined structures using SiGe sacrificial layers.

単層ポリシリコン電極を採用した高感度１／４型（対角４．５ｍｍ）３６万画素ＦＴ‐ＣＣＤイメージセンサ

We experimentally fabricated a frame transfer CCD (FT-CCD) image sensor for Recommendation ITU-R BT, 601 with a single-layer poly-silicon electrode structure.We set the gap to 0.45 pm to balance charge-handling capability against optical sensitivity. We optimized the membrane structure to improve optical sensitivity. We sandwiched the poly-silicon gate between two silicon-nitride layers with a high refractive index to suppress reflection on the poly-silicon surface. The sensitivity was improved 40% with this structure. An FT-CCD image sensor constructed using this new structure is very simple and has high performance.

Low-impedance thin-film polycrystalline silicon microelectrodes for extracellular stimulation and recording

Polycrystalline silicon thin films were explored with respect to their application as low-impedance microelectrodes for extracellular stimulation and recording of cells. Microelectrode arrays (MEAs) comprising polysilicon microelectrodes were fabricated using CMOS-compatible processes. Overall capacitance of an electrode with a diameter of 20 μm is on the order of 200–300 pF. Chemical and morphological stability in physiological saline solution was excellent over a period of at least 5 months. This finding renders applications in neuronal implants or bio-chips. Nanoporous polysilicon electrodes were created by anodic oxidation in hydrofluoric acid (HF). However, no considerable decrease of electrode impedance was observed although pore formation was clearly confirmed by transmission electron microscopy (TEM).

Morphology and Integration of Rough Polycrystalline Silicon Films for DRAM Storage Cell Applications

This study evaluates the important aspects of deposition and integration of rough polycrystalline silicon films for dynamic random acces memory (DRAM) storage capacitor applications. Electrical performance of rough polycrystalline films is investigated in terms of grain morphology and microstructural control. It is shown that the morphology, roughness, and doping of the films strongly affect the capacitor electrical performance. A strong correlation is observed between the surface roughness measured in terms of reflectance and the electrical area enhancement factor (AEF) of the films. Leakage current performance of rough and control/smooth electrode devices incorporating NO dielectric is evaluated. The results demonstrate that the leakage current density of the devices with rough electrode is less than the AEF times the leakage current density of the devices with control polysilicon electrode. Various integration approaches to fabricate the rough polysilicon storage electrode are examined. Lower thermal budget processing sequences are shown to be viable options. Rapid thermal based doping and dopant activation anneal processes are demonstrated as alternatives to high temperature furnace annealing sequences. Capacitance‐voltage data is presented with AEF and dopant depletion analysis for devices incorporating lower thermal budget sequences. It is shown that phosphine gas‐doping of the rough polysilicon electrode increases the AEF by 17% as a consequence of the doping process. © 1999 The Electrochemical Society. All rights reserved.

Influence of Interface Structure on Chemical Etching Process for Air Gap of Microelectromechanical System Based on Surface Micromachining

This paper analyses the problems posed by the interface structure during chemical etching by Hydro-fluoric (HF) acid for creating air gaps in microelectromechnical system (MEMS) devices using PZT(53/47) films and surface micromachining techniques. In order to investigate the influence of interface structure on the HF chemical etching process, Pt/PZT/Pt/Ti/TiO2/polysilicon/Si3N4/PSG/Si (Samples A and C) and Pt/PZT/RuO2/Ru/Si3N4/PSG/Si (Sample B) structures were fabricated. These structures are selected for a microcantilever beam and/or an uncooled IR detectors fabricated with PZT piezoelectric/pyroelectric films based on the surface micromachining technique. Both need etching for the removal of phosphor silicate glass (PSG) to create an air gap. If the devices had a poor interface structure, they would fail during the HF chemical etching process because the poor interface structure would act as a kind of penetration path for etching acid leading to unwanted etching. Therefore, it is very important to investigate the interface structure to fabricate efficient MEMS devices. In this study two different solutions have been suggested to improve the interface structure. The first is post thermal annealing at 900°C for 30 min. after deposition of polycrystalline silicon for sample A. Secondly, a RuO2/Ru hybrid electrode was deposited on Si3N4 directly instead of on the Pt/Ti/TiO2/Polysilicon electrode, which has Pt/PZT/RuO2/Ru/Si3N4/PSG/Si as the device structure. These two solutions suggest that a dense interface structure increases enhances of success of the chemical etching process of MEMS devices fabricated using PZT films and surface micromachining techniques.

Evaluation of the dielectric breakdown of reoxidized nitrided oxide (ONO) in flash memory devices using constant current-stressing technique

The dielectric breakdown time of reoxidized nitrided oxide (ONO) in flash memory devices has been evaluated using the constant current-stressing technique. The dielectric performance of ONO was severely impaired by the stressing effects of a current. A positive constant current of 5 μA stressing on a 280 Åthick ONO layer (via two polysilicon electrodes), covering an area of 50,000 μm 2 took only a mere 20 s to breakdown. The situation worsened when a negative current of 5 μA was stressed on it—the ONO layer almost instantaneously broke down. The electrical tolerance of the ONO interpoly dielectric is still mediocre upon stressing with a smaller current. With a 1 μA positive constant current-stressing test, the average breakdown time of the dielectric layer was about 50 s, but it broke down instantaneously again upon a 1 μA negative constant current-stressing test. The probable causes for the rapid degradation of ONO dielectric properties are the rough surface of bottom polysilicon layer, the trapped fluoride ions in the device, and the changes in the occupancy of the interfacial states. There can be the occurrence of current surging through the devices during their fabrication e.g. stack-etching. Hence, with the future scaling of memory devices, situations of higher current density surging through the devices will be realized. It will be beneficial to investigate how the ONO layer conducts upon current-stressing. The constant current-stressing technique is a simple and most straightforward method to address and simulate the current-stressing conditions.

A tunable vibratory microgyroscope

A tunable vibratory microgyroscope has been fabricated by surface-micromachining technology. The 7.5 μm thick polysilicon structural layer is deposited using LPCVD at 625 °C. The resonance frequency in the detection mode is designed to be higher than that in the driving mode so that the gyroscope could be matched to the resonance frequencies by applying an inter-plate d.c. bias. The gyroscope is driven in a resonant state by electrostatic force and the output detected is due to a capacitance change between the plate and the polysilicon electrode. The resonance frequencies of the gyroscope in the driving and detection directions are measured to be 10.48 and 10.93 kHz, respectively. The resonance frequency in the detection direction can be shifted to 10.52 kHz by applying a tuning voltage of 4.0 V. The quality factor and resonance frequency of the detection mode are significantly affected by ambient pressure. The electrical noise equivalent rate of this device is about 0.1 ° s −1 at 10 −2 torr.

Fabrication and Electrical Characteristics of Single Electron Tunneling Devices Based on Si Quantum Dots Prepared by Plasma Processing

This paper presents results on the fabrication of single electron tunneling devices using silicon nanocrystals. We prepare silicon nanocrystals of uniform particle size by very-high-frequency plasma processing and deposit them on a poly-silicon electrode structure having a very small inter-electrode separation of 26–70 nm. Current-voltage (I–V) characteristics show Coulomb blockade and Coulomb staircase at 77 K. For very narrow electrode separation, Coulomb staircase appears in I-V characteristics even at room temperature.

Evaluation of Electron Shading Charge Buildup Damage Using Metal-Nitride-Oxide-Silicon Capacitors

The damage from plasma-induced charge buildup caused by the “electron shading” effect was investigated in a pulse-modulated plasma using metal-nitride-oxide-silicon (MNOS) capacitors. The reduction of charge buildup depends strongly on the on-time. When the on-time is shorter than 50 µ s and the off-time is constant at 100 µ s, the potential difference between high and low aspect ratio patterns, ΔV, becomes zero. However, the shift in the flatband voltage is large in the case of 33.3 µ s on-time, and it corresponds to the degradation of the gate oxide. The potential of the silicon substrate is thought to become low compared to the polysilicon electrode. This indicates that the potential of the silicon substrate must also be controlled.

Evaluation of the gate oxide transformed by ion implantation

Ion implantation-induced damage to the gate oxide of antenna MOS capacitors has been investigated. It is confirmed that ion implantation into the MOS capacitors causes charge-induced damage and ion bombardment-induced damage. The degradation of the gate oxide due to ion implantation varies according to the relation between the projected range and the thickness of the polysilicon electrode. The mechanism of the oxide damage is discussed based on the results of current-voltage measurements and structural analyses by ESR and FTIR-ATR.