poly-Si Thin Film Research Articles

镍硅化物诱导横向晶化制备高性能多晶硅薄膜晶体管

镍硅化物诱导横向晶化制备高性能多晶硅薄膜晶体管

High performance poly-Si thin film transistors fabricated by self-aligned seed induced lateral crystallization

In this study, a low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) was fabricated by self-aligned silicide seed induced lateral crystallization (SA-SILC). In comparison with a self-aligned metal induced lateral crystallization (SA-MILC) TFT, the SA-SILC TFT showed better electrical properties. In particular, the leakage current was decreased by SA-SILC at high drain voltages. It was found that the Ni rich phase between the channel and drain junction region acted as trapping sites to generate leakage current by thermionic field emission. After applying the SA-SILC process, the p-channel polycrystalline silicon (poly-Si) TFT exhibited a mobility of 67 cm 2/V·s, a minimum leakage current of 2.6 × 10−11 A at V D = −5 V, a subthreshold slope of 0.8 V/dec, and a maximum on/off ratio of 7.0 × 10 6, together resulting in a high-performance device that surpasses the conventional SA-MILC poly-Si TFT.

Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Charge Trapping Layer

This study investigates the characteristics of the planar twin poly-Si thin film transistor (TFT) EEPROM that utilizes a nitride (Si3N4) charge trapping layer. A comparison is made of two devices with different gate dielectrics, one a 16 nm-thick oxide (SiO2) layer for O-structure and the other 5 nm/10 nm-thick oxide/nitride layers for O/N-structure. Incorporating a nitride charge trapping layer and reducing the tunneling oxide thickness enable the O/N-structure EEPROM to enhance the program/erase (P/E) efficiency. Additionally, EEPROM formed with the tri-gate nanowires (NWs) structure can further enhance P/E efficiency and a large memory window because of its high electric field across the tunneling oxide. Reliability results indicated that, since the nitride layer contains discrete traps, the memory window can be maintained 2.2 V after 10(4) P/E cycles. For retention, the memory window can be maintained 1.9 V, and 30% charge loss for ten years of data storage. This investigation indicates that its possibility in future system-on-panel (SOP) of thin-film transistor liquid crystal display (TFTLCD) and 3-D stacked high-density Flash memory applications.

Liquid-phase explosive crystallization of electron-beam-evaporated a-Si films induced by flash lamp annealing

We succeed in the formation of micrometer-order-thick polycrystalline silicon (poly-Si) films through the flash-lamp-induced liquid-phase explosive crystallization (EC) of precursor a-Si films prepared by electron-beam (EB) evaporation. The velocity of the explosive crystallization (vEC) is estimated to be ∼14m/s, which is close to the velocity of the liquid-phase epitaxy (LPE) of Si at a temperature around the melting point of a-Si of 1418K. Poly-Si films formed have micrometer-order-long grains stretched along a lateral crystallization direction, and X-ray diffraction (XRD) and electron diffraction pattern measurements reveal that grains in poly-Si films tend to have a particular orientation. These features are significantly different from our previous results: the formation of poly-Si films containing randomly-oriented 10-nm-sized fine grains formed from a-Si films prepared by catalytic chemical vapor deposition (Cat-CVD) or sputtering. One possible reason for the emergence of a different EC mode in EB-evaporated a-Si films is the suppression of solid-phase nucleation (SPN) during Flash Lamp Annealing (FLA) due to tensile stress which precursor a-Si films originally hold. Poly-Si films formed from EB-evaporated a-Si films would contribute to the realization of high-efficiency thin-film poly-Si solar cells because of large and oriented grains.

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN x /SiO 2 gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN x /SiO 2) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (Δ V TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.

A Physics-Based Effective Mobility Model for Polycrystalline Silicon Thin Film Transistor Considering Discontinuous Energy Band at Grain Boundaries

A physics-based effective mobility model for polycrystalline silicon (poly-Si) thin film transistor (TFT) is developed by considering the discontinuous energy band between grain and grain boundary and Gaussian energy distribution at grain boundary. Three conduction mechanisms, thermionic-emission effect, drift-diffusion effect and tunneling effect, are introduced to describe the mobility. It is found that the physical factors, such as the trapped state distribution at grain boundary, the additional potential barrier, the rate of carriers' thermal velocity to diffusion velocity and the in-grain quality, have a strong influence on the effective mobility of poly-Si TFT and would not be neglected or replaced by some fitting parameters. The proposed model provides an accurate and analytical description for the effective mobility of poly-Si TFT. The calculated results of the proposed model are verified by the experimental data.

Ni-Induced Lateral Fast Crystallization of Amorphous Silicon Film by Microwave Annealing

Polycrystalline Si (poly-Si) thin films for application to display devices and solar cell are generally fabricated by crystallizing amorphous Si (a-Si) thin film precursors. In this paper, studies on Ni-induced lateral crystallization of a-Si thin films by microwave annealing at low temperature were reported. The crystallization of a-Si thin films was enhanced by applying microwaves to the films. The poly-Si films were invested by Optical Microscopy, X-ray Diffraction (XRD) , Raman Spectroscopy and Scanning Electron Microscope(SEM). After processing of Ni-induced lateral crystallization by microwave annealing above 500°C, the a-Si has begun to be crystallized with large grains having the main (111) orientation. The rate of crystallization at 550°C is about 0.033μm/min. Compared to Ni-induced lateral crystallization by conventional furnace annealing, Ni-induced lateral crystallization by microwave annealing both lowers the crystallization temperature and reduces the time of crystallization. The crystallization mechanism during microwave annealing was also studied. The technique that combines Ni-induced lateral crystallization with microwave annealing has potential applications in thin-film transistors (TFT’s) and solar cell.

Low temperature processing of a large grain polycrystalline silicon thin film on soda-lime glass

We have demonstrated that a polycrystalline silicon thin film can be fabricated in situ on soda-lime glass at 450 °C by an Al-induced crystallization method using electron beam evaporation. The catalytic Al is found to diffuse to the top of the crystallized Si layer and can be easily etched away by a mixture of acids. This low temperature Si crystallization process is well explained by thermodynamic consideration. Subsequent annealing at the same temperature (450 °C) for 6 h improves the crystallinity of the film and enlarges the average grain size to over 5 µm. There are no observable impurity phases. The poly-Si thin films are (1 1 1) oriented and all the grains are well aligned. A defect-free and excellent crystalline structure has been revealed by transmission electron microscopy. The measured resistivity, carrier concentration and charge mobility of these as-prepared poly-Si thin films indicate that our present low temperature processing technique has great advantage and prospect for the photonics industry.

Influence of Grain Size Deviation on the Characteristics of Poly-Si Thin Film Transistor

Influence of Grain Size Deviation on the Characteristics of Poly-Si Thin Film Transistor

Seed-Free Fabrication of Highly Bi-Axially Oriented Poly-Si Thin Films by Continuous-Wave Laser Crystallization with Double-Line Beams

Highly bi-axially oriented poly-Si thin films with very long grains (>100 μm) were successfully fabricated on quartz substrates by continuous wave laser crystallization with parallel double-line beams, without seed crystals. The newly-developed technique restricts crystal nucleation time and enhances growth of crystal nuclei of a specific orientation selectively, which is preferentially generated. The technique achieved highly-oriented silicon grains having (110), (111) and (211) crystal orientations in the laser lateral crystallized plane, the transverse side plane and the surface plane, respectively. All the silicon grains were elongated in the laser-scanning direction and linearly arranged with a length of over 100 μm and a width of 0.7 μm. The laser-crystallized poly-Si films were crystallographically investigated precisely, and electrically inactive CSL Σ3 twin boundaries were typically observed. This technique enables simultaneous enhancement of grain size and control of crystal orientation.

Characteristics of various instability in Ni-FALC poly-Si thin film transistors

In this study, the characteristics of positive bias temperature instability (PBTI) and cyclic constant voltage stress (CVS) in thin film transistors (TFTs) incorporating Ni-FALC poly-Si film were investigated under various stress conditions. In PBTI, the threshold voltage ( V TH) was degraded by a vertical electric field on the gate stack, and an abrupt variation of V TH was attributed to the creation of defects in the gate oxide and the increase of the effective interface trap state. In contrast to the formation of defects, the poly-Si film was not sensitive to PBTI stress (the fluctuation in the grain boundary trap density was just 5.6%). In two-cycle CVS of devices before and after O 2 plasma treatment, the direction of the V TH shift and polarity of bias showed good correlation. In particular, the O 2 plasma-treated device demonstrated low Subthreshold swing (S.S) and low minimum drain current compared to the untreated one. The improvement of device performance seemed to originate from the reduction of effective interface trap sites and leakage current paths.

A novel optical diagnostic technique for analyzing the recrystallization characteristics of polycrystalline silicon thin films following frontside and backside excimer laser irradiation

Excimer laser annealing (ELA) is a widely used technique for producing polycrystalline silicon (poly-Si) thin films. An optical inspection system with simple optical arrangements for rapid measurement of recrystallization results of poly-Si thin films is developed in this study. The recrystallization results after both frontside ELA and backside ELA can be easily visible from the profile of peak power density distribution using the optical inspection system developed with an optimized moving velocity of 0.312 mm/s of the specimen. The method of backside ELA is suggested for batch production of low-temperature polycrystalline silicon thin-film transistors due to higher laser beam utilization efficiency and lower surface roughness of poly-Si films.

Deposition of polycrystalline Si thin films on glass substrates by direct negative Si ion beam deposition

Polycrystalline Si (Poly-Si) thin films were deposited on a glass substrate by direct negative Si (Si −) ion beam deposition. The glass substrate temperature was kept constant at 500 °C for all depositions. Prior to deposition, the ion energy spread and ion-to-atom arrival ratio were evaluated as a function of the ion beam energy. The Si − ion energy spread was less than 10% regardless of the ion energy, while the ion-to-atom arrival ratio increased proportionally from 1.3 to 1.6 according to the ion beam energy. Atomic force microscopy images showed that a relatively rough surface was obtained at 50 eV of Si − ion energy and it is also concluded that the Si − ion beam irradiation at 50 eV is effective to deposit Si thin film with small grains as shown in Fig. 3.

P‐30: Artificial Retina using Poly‐Si Thin‐Film Transistors driven by Wireless Power Supply

AbstractWe have developed an artificial retina using poly‐Si thin‐film transistors driven by wireless power supply. It is found that the illumination profile can be correctly detected as the output voltage profile even if it is driven using unstable power source generated by inductive coupling, diode bridge, and Zener diodes. This means the feasibility to implant the artificial retina into human eyeballs.

Characteristic Degradation of Poly-Si Thin-Film Transistors With Large Grains From the Viewpoint of Grain Boundary Location

The characteristic degradation of poly-Si thin-film transistors (TFTs) with large grains has been analyzed from the viewpoint of grain boundary location. Only when the grain boundary is located near the drain junction during bias stress, trap states are generated there due to the hot carriers, and the TFTs are severely degraded. Moreover, in the linear region, the transistor characteristics are degraded wherever the grain boundary is located. On the other hand, in the saturation region, the transistor characteristics are degraded when the grain boundary is located near the source junction, whereas the transistor characteristics are not degraded very much when the grain boundary is located near the drain junction. This paper is the first report to give an experimental example of the aforementioned phenomenon, which was conjectured using 2-D device simulation.

Study on Poly-Si Thin Films by Vacuum Evaporation

The process of Vacuum Evaporation and characteristic of poly-Si thin film on different kinds of substrates (copper and glass) are studied in this thesis. The samples were characterized by TEM, AFM and metallographic microscope. The result indicates that the samples after annealing treatment are polycrystalline. Thin film on copper substrate shows better properties in degree of crystallization, grain smoothness, compact density and uniformity. The thickness of thin films on both copper and glass substrates is 1.2µm.The grain size ranges from 0.1~0.15µm.And the pressure-resisting value of the poly-Si thin film is 384.2V.

In situ Observation of Polycrystalline Silicon Thin Films Grown Using Aluminum-Doped Zinc Oxide on Glass Substrate by the Aluminum-Induced Crystallization

We present the impact of Al-doped ZnO (AZO) layer of polycrystalline silicon (poly-Si) thin films grown at different annealing temperatures using aluminum-induced crystallization (AIC). In situ observation revealed that the increase of crystallized fraction was fast in poly-Si films grown with AZO layer compared to those without AZO. It is explained that the roughness of interface between Si and Al by introducing AZO layer was increased, which contributes to enhancement of diffused Si concentration into Al layer. Those results were also quantitatively demonstrated by calculating of Si concentration diffused into the Al layer. Therefore, we exhibit that controlling interface roughness is shown to be important to determine the growth rate of poly-Si thin films.

The effect of dielectric spacer thickness on surface plasmon enhanced solar cells for front and rear side depositions

The excitation of surface plasmons on metallic nanoparticles has the potential to significantly improve the performance of solar cells, in particular thin-film structures. In this article, we investigate the effect of the dielectric spacer layer thickness on the photocurrent enhancement of 2 μm thick, thin-film poly-Si on glass solar cells, due to random arrays of self-assembled Ag nanoparticles deposited on the front or the rear of the cells. We report a strong asymmetry in the external quantum efficiency (EQE) of the cell for front and rear located particles for different spacer thicknesses, which is attributed to differences in the scattering behavior of the nanoparticles. We find that for random arrays, with spectrally broad scattering resonances, the strength of the driving field and the coupling efficiency are more important for light trapping than the resonance wavelength. For particles located on the front of the cells it is desirable to have a thin dielectric spacer layer to enhance the scattering from the Ag nanoparticles. Additionally, light trapping provided by the random sized particles on the front can overcome suppression of light transmitted in the visible wavelength regions for thin layers of Si, to result in overall EQE enhancements. However, for particles deposited on the rear it is more beneficial to have the particles as close to the Si substrate as possible to increase both the scattering and the coupling efficiency.

Non-destructive measurements on recrystallization and grain-size characterization of polycrystalline silicon

Excimer-laser annealing is a widely used technique for producing polycrystalline silicon thin films. We develop an optical inspection system with simple optical arrangements for rapid measurement of recrystallization and grain-size characterization of poly-Si thin films. The recrystallization characterization of the sample after excimer-laser annealing can be easily manifested directly by the profile of peak-power density distribution. We investigate the relation between the maximum grain size of poly-Si thin films and transmission of the optical measurements and find that it coincides with those obtained by field-emission scanning electron microscopy.

Effect on Thickness of Al Layer in Poly-Crystalline Si Thin Films Using Aluminum(Al) Induced Crystallization Method

The polycrystalline silicon (poly-Si) thin films were prepared by aluminum induced crystallization. Aluminum (Al) and amorphous silicon (a-Si) layers were deposited using DC sputtering and plasma enhanced chemical vapor deposition method, respectively. For the whole process Al properties of bi-layers can be one of the important factors. In this paper we investigated the structural and electrical properties of poly-crystalline Si thin films with a variation of Al thickness through simple annealing process. All samples showed the polycrystalline phase corresponding to (111), (311) and (400) orientation. Process time, defined as the time required to reach 95% of crystalline fraction, was within 60 min and Al(200 nm)/a-Si(400 nm) structure of bi-layer showed the fast response for the poly-Si films. The conditions with a variation of Al thickness were executed in preparing the continuous poly-Si films for solar cell application.