PLL Output Research Articles

Konzeption und Demonstration eines Frequenzsynthesizers für das Ku-Band mit modernen Frequenzaufbereitungsmethoden

The following report describes the development and design of a modern synthesizer architecture generating a signal in the Ku-band between 12 and 19 GHz. State-of-the-art techniques as direct digital synthesizer (DDS) and wide-band PLL are used. The direct digital synthesizer generates an output frequency in the range of 9.5-10.5 MHz with a resolution better than 10 mHz. The high frequency resolution allows frequency steps smaller than 15 Hz in the Ku-band. The output signal of the direct digital synthesizer is used as a reference by a wide-band PLL with a phase stabilized output frequency in the range of 0.8-1.6 GHz. The PLL output signal is multiplied by factors 2 and 3 to an higher frequency. In the last block this frequency spanning between 0.95-4.30 GHz is up-converted and multiplied to the Ku-band. This project was possible through a cooperation between the Institut fur Hochleistungs-impuls- und Mikrowellentechnik an institution of the Forschungszentrum Karlsruhe, and the Institut fur Hochstfrequenztechnik und Elektronik of the University of Karlsruhe.

Charge pump with perfect current matchingcharacteristics in phase-locked loops

Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an error amplifier and reference current sources, one can achieve a charge pump with good current matching characteristics. It shows nearly perfect current matching characteristics over the whole VCO input range, and the amount of the reference spur is < –75 dBc in the PLL output signal. The charge pump circuit is implemented in a 0.25 µm CMOS process.

A novel digital signal processing bit synchronizer for a prml recording channel

AbstractThe partial‐response maximum likelihood (PRML) system currently is investigated for practical applications as a modulation/demodulation scheme for digital magnetic recording equipment.This paper proposes a construction of the bit synchronizer by complete digital signal processing. The operational principle is verified by experiment. The proposed bit synchronizer is composed of the decision‐feedback digital PLL and the interpolator. The decision‐feedback digital PLL receives the data‐asynchronous sampled signal sequence as the input, which is the result of sampling by the fixed clock of two samples/bit, and regenerates the clock. The interpolator calculates the signal value at the data point indicated by the phase of the decision‐feedback digital PLL output. The result is given to the Viterbi decoder.By applying the proposed scheme, the PRML demodulator from the equalizer to the Viterbi decoder can be realized as a digital signal processing circuit, which operates synchronously with the single fixed master clock. A PRML demodulator is constructed based on the proposed bit synchronizer, and the operational principle is verified by an experiment using a magnetic disk device. The bit‐error rate less than 10−6 is obtained for the channel bit rate of 10 Mbps.